ARM: sun5i: Add DRAM gates
The DRAM gates control whether the image / display devices on the SoC have access to the DRAM clock or not. Enable it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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@ -61,7 +61,8 @@
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0";
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clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
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clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
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<&dram_gates 26>;
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status = "disabled";
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};
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};
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@ -149,6 +150,26 @@
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"apb1_i2c2", "apb1_uart1",
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"apb1_uart3";
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};
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dram_gates: clk@01c20100 {
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#clock-cells = <1>;
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compatible = "allwinner,sun5i-a13-dram-gates-clk",
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"allwinner,sun4i-a10-gates-clk";
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reg = <0x01c20100 0x4>;
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clocks = <&pll5 0>;
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clock-indices = <0>,
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<1>,
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<25>,
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<26>,
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<29>,
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<31>;
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clock-output-names = "dram_ve",
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"dram_csi",
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"dram_de_fe",
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"dram_de_be",
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"dram_ace",
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"dram_iep";
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};
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};
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soc@01c00000 {
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@ -52,7 +52,7 @@
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0-tve0";
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clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
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<&ahb_gates 44>;
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<&ahb_gates 44>, <&dram_gates 26>;
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status = "disabled";
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};
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};
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