[POWERPC] spufs: further abstract priv1 register access
To support muti-platform binaries the spu hypervisor accessor routines must have runtime binding. I removed the existing statically linked routines in spu.h and spu_priv1_mmio.c and created new accessor routines in spu_priv1.h that operate indirectly through an ops struct spu_priv1_ops. spu_priv1_mmio.c contains the instance of the accessor routines for running on raw hardware. Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Geoff Levand
Paul Mackerras
parent
c01ea72a3b
commit
540270d82d
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@ -49,6 +49,7 @@
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#include <asm/ppc-pci.h>
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#include <asm/irq.h>
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#include <asm/spu.h>
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#include <asm/spu_priv1.h>
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#include "interrupt.h"
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#include "iommu.h"
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@ -83,6 +84,9 @@ static void __init cell_setup_arch(void)
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{
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ppc_md.init_IRQ = iic_init_IRQ;
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ppc_md.get_irq = iic_get_irq;
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#ifdef CONFIG_SPU_BASE
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spu_priv1_ops = &spu_priv1_mmio_ops;
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#endif
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cbe_regs_init();
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@ -34,10 +34,15 @@
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#include <asm/prom.h>
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#include <linux/mutex.h>
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#include <asm/spu.h>
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#include <asm/spu_priv1.h>
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#include <asm/mmu_context.h>
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#include "interrupt.h"
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const struct spu_priv1_ops *spu_priv1_ops;
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EXPORT_SYMBOL_GPL(spu_priv1_ops);
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static int __spu_trap_invalid_dma(struct spu *spu)
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{
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pr_debug("%s\n", __FUNCTION__);
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@ -1,133 +1,155 @@
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/*
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* access to SPU privileged registers
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* spu hypervisor abstraction for direct hardware access.
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*
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* (C) Copyright IBM Deutschland Entwicklung GmbH 2005
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* Copyright 2006 Sony Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/module.h>
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#include <asm/io.h>
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#include <asm/spu.h>
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#include <asm/spu_priv1.h>
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void spu_int_mask_and(struct spu *spu, int class, u64 mask)
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static void int_mask_and(struct spu *spu, int class, u64 mask)
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{
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u64 old_mask;
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old_mask = in_be64(&spu->priv1->int_mask_RW[class]);
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out_be64(&spu->priv1->int_mask_RW[class], old_mask & mask);
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}
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EXPORT_SYMBOL_GPL(spu_int_mask_and);
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void spu_int_mask_or(struct spu *spu, int class, u64 mask)
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static void int_mask_or(struct spu *spu, int class, u64 mask)
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{
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u64 old_mask;
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old_mask = in_be64(&spu->priv1->int_mask_RW[class]);
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out_be64(&spu->priv1->int_mask_RW[class], old_mask | mask);
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}
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EXPORT_SYMBOL_GPL(spu_int_mask_or);
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void spu_int_mask_set(struct spu *spu, int class, u64 mask)
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static void int_mask_set(struct spu *spu, int class, u64 mask)
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{
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out_be64(&spu->priv1->int_mask_RW[class], mask);
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}
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EXPORT_SYMBOL_GPL(spu_int_mask_set);
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u64 spu_int_mask_get(struct spu *spu, int class)
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static u64 int_mask_get(struct spu *spu, int class)
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{
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return in_be64(&spu->priv1->int_mask_RW[class]);
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}
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EXPORT_SYMBOL_GPL(spu_int_mask_get);
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void spu_int_stat_clear(struct spu *spu, int class, u64 stat)
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static void int_stat_clear(struct spu *spu, int class, u64 stat)
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{
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out_be64(&spu->priv1->int_stat_RW[class], stat);
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}
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EXPORT_SYMBOL_GPL(spu_int_stat_clear);
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u64 spu_int_stat_get(struct spu *spu, int class)
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static u64 int_stat_get(struct spu *spu, int class)
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{
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return in_be64(&spu->priv1->int_stat_RW[class]);
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}
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EXPORT_SYMBOL_GPL(spu_int_stat_get);
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void spu_int_route_set(struct spu *spu, u64 route)
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static void int_route_set(struct spu *spu, u64 route)
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{
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out_be64(&spu->priv1->int_route_RW, route);
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}
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EXPORT_SYMBOL_GPL(spu_int_route_set);
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u64 spu_mfc_dar_get(struct spu *spu)
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static u64 mfc_dar_get(struct spu *spu)
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{
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return in_be64(&spu->priv1->mfc_dar_RW);
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}
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EXPORT_SYMBOL_GPL(spu_mfc_dar_get);
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u64 spu_mfc_dsisr_get(struct spu *spu)
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static u64 mfc_dsisr_get(struct spu *spu)
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{
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return in_be64(&spu->priv1->mfc_dsisr_RW);
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}
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EXPORT_SYMBOL_GPL(spu_mfc_dsisr_get);
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void spu_mfc_dsisr_set(struct spu *spu, u64 dsisr)
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static void mfc_dsisr_set(struct spu *spu, u64 dsisr)
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{
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out_be64(&spu->priv1->mfc_dsisr_RW, dsisr);
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}
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EXPORT_SYMBOL_GPL(spu_mfc_dsisr_set);
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void spu_mfc_sdr_set(struct spu *spu, u64 sdr)
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static void mfc_sdr_set(struct spu *spu, u64 sdr)
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{
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out_be64(&spu->priv1->mfc_sdr_RW, sdr);
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}
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EXPORT_SYMBOL_GPL(spu_mfc_sdr_set);
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void spu_mfc_sr1_set(struct spu *spu, u64 sr1)
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static void mfc_sr1_set(struct spu *spu, u64 sr1)
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{
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out_be64(&spu->priv1->mfc_sr1_RW, sr1);
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}
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EXPORT_SYMBOL_GPL(spu_mfc_sr1_set);
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u64 spu_mfc_sr1_get(struct spu *spu)
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static u64 mfc_sr1_get(struct spu *spu)
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{
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return in_be64(&spu->priv1->mfc_sr1_RW);
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}
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EXPORT_SYMBOL_GPL(spu_mfc_sr1_get);
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void spu_mfc_tclass_id_set(struct spu *spu, u64 tclass_id)
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static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id)
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{
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out_be64(&spu->priv1->mfc_tclass_id_RW, tclass_id);
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}
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EXPORT_SYMBOL_GPL(spu_mfc_tclass_id_set);
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u64 spu_mfc_tclass_id_get(struct spu *spu)
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static u64 mfc_tclass_id_get(struct spu *spu)
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{
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return in_be64(&spu->priv1->mfc_tclass_id_RW);
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}
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EXPORT_SYMBOL_GPL(spu_mfc_tclass_id_get);
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void spu_tlb_invalidate(struct spu *spu)
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static void tlb_invalidate(struct spu *spu)
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{
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out_be64(&spu->priv1->tlb_invalidate_entry_W, 0ul);
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}
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EXPORT_SYMBOL_GPL(spu_tlb_invalidate);
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void spu_resource_allocation_groupID_set(struct spu *spu, u64 id)
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static void resource_allocation_groupID_set(struct spu *spu, u64 id)
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{
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out_be64(&spu->priv1->resource_allocation_groupID_RW, id);
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}
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EXPORT_SYMBOL_GPL(spu_resource_allocation_groupID_set);
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u64 spu_resource_allocation_groupID_get(struct spu *spu)
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static u64 resource_allocation_groupID_get(struct spu *spu)
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{
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return in_be64(&spu->priv1->resource_allocation_groupID_RW);
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}
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EXPORT_SYMBOL_GPL(spu_resource_allocation_groupID_get);
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void spu_resource_allocation_enable_set(struct spu *spu, u64 enable)
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static void resource_allocation_enable_set(struct spu *spu, u64 enable)
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{
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out_be64(&spu->priv1->resource_allocation_enable_RW, enable);
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}
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EXPORT_SYMBOL_GPL(spu_resource_allocation_enable_set);
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u64 spu_resource_allocation_enable_get(struct spu *spu)
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static u64 resource_allocation_enable_get(struct spu *spu)
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{
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return in_be64(&spu->priv1->resource_allocation_enable_RW);
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}
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EXPORT_SYMBOL_GPL(spu_resource_allocation_enable_get);
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const struct spu_priv1_ops spu_priv1_mmio_ops =
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{
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.int_mask_and = int_mask_and,
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.int_mask_or = int_mask_or,
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.int_mask_set = int_mask_set,
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.int_mask_get = int_mask_get,
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.int_stat_clear = int_stat_clear,
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.int_stat_get = int_stat_get,
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.int_route_set = int_route_set,
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.mfc_dar_get = mfc_dar_get,
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.mfc_dsisr_get = mfc_dsisr_get,
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.mfc_dsisr_set = mfc_dsisr_set,
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.mfc_sdr_set = mfc_sdr_set,
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.mfc_sr1_set = mfc_sr1_set,
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.mfc_sr1_get = mfc_sr1_get,
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.mfc_tclass_id_set = mfc_tclass_id_set,
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.mfc_tclass_id_get = mfc_tclass_id_get,
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.tlb_invalidate = tlb_invalidate,
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.resource_allocation_groupID_set = resource_allocation_groupID_set,
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.resource_allocation_groupID_get = resource_allocation_groupID_get,
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.resource_allocation_enable_set = resource_allocation_enable_set,
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.resource_allocation_enable_get = resource_allocation_enable_get,
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};
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@ -32,6 +32,7 @@
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#include <asm/io.h>
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#include <asm/spu.h>
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#include <asm/spu_priv1.h>
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#include <asm/spu_csa.h>
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#include <asm/mmu_context.h>
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#include "spufs.h"
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@ -46,6 +46,7 @@
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#include <asm/io.h>
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#include <asm/spu.h>
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#include <asm/spu_priv1.h>
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#include <asm/spu_csa.h>
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#include <asm/mmu_context.h>
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@ -183,29 +183,6 @@ static inline void unregister_spu_syscalls(struct spufs_calls *calls)
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#endif /* MODULE */
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/* access to priv1 registers */
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void spu_int_mask_and(struct spu *spu, int class, u64 mask);
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void spu_int_mask_or(struct spu *spu, int class, u64 mask);
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void spu_int_mask_set(struct spu *spu, int class, u64 mask);
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u64 spu_int_mask_get(struct spu *spu, int class);
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void spu_int_stat_clear(struct spu *spu, int class, u64 stat);
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u64 spu_int_stat_get(struct spu *spu, int class);
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void spu_int_route_set(struct spu *spu, u64 route);
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u64 spu_mfc_dar_get(struct spu *spu);
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u64 spu_mfc_dsisr_get(struct spu *spu);
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void spu_mfc_dsisr_set(struct spu *spu, u64 dsisr);
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void spu_mfc_sdr_set(struct spu *spu, u64 sdr);
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void spu_mfc_sr1_set(struct spu *spu, u64 sr1);
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u64 spu_mfc_sr1_get(struct spu *spu);
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void spu_mfc_tclass_id_set(struct spu *spu, u64 tclass_id);
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u64 spu_mfc_tclass_id_get(struct spu *spu);
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void spu_tlb_invalidate(struct spu *spu);
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void spu_resource_allocation_groupID_set(struct spu *spu, u64 id);
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u64 spu_resource_allocation_groupID_get(struct spu *spu);
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void spu_resource_allocation_enable_set(struct spu *spu, u64 enable);
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u64 spu_resource_allocation_enable_get(struct spu *spu);
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/*
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* This defines the Local Store, Problem Area and Privlege Area of an SPU.
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*/
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@ -0,0 +1,182 @@
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/*
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* Defines an spu hypervisor abstraction layer.
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*
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* Copyright 2006 Sony Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#if !defined(_SPU_PRIV1_H)
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#define _SPU_PRIV1_H
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#if defined(__KERNEL__)
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struct spu;
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/* access to priv1 registers */
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struct spu_priv1_ops
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{
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void (*int_mask_and) (struct spu *spu, int class, u64 mask);
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void (*int_mask_or) (struct spu *spu, int class, u64 mask);
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void (*int_mask_set) (struct spu *spu, int class, u64 mask);
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u64 (*int_mask_get) (struct spu *spu, int class);
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void (*int_stat_clear) (struct spu *spu, int class, u64 stat);
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u64 (*int_stat_get) (struct spu *spu, int class);
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void (*int_route_set) (struct spu *spu, u64 route);
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u64 (*mfc_dar_get) (struct spu *spu);
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u64 (*mfc_dsisr_get) (struct spu *spu);
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void (*mfc_dsisr_set) (struct spu *spu, u64 dsisr);
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void (*mfc_sdr_set) (struct spu *spu, u64 sdr);
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void (*mfc_sr1_set) (struct spu *spu, u64 sr1);
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u64 (*mfc_sr1_get) (struct spu *spu);
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void (*mfc_tclass_id_set) (struct spu *spu, u64 tclass_id);
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u64 (*mfc_tclass_id_get) (struct spu *spu);
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void (*tlb_invalidate) (struct spu *spu);
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void (*resource_allocation_groupID_set) (struct spu *spu, u64 id);
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u64 (*resource_allocation_groupID_get) (struct spu *spu);
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void (*resource_allocation_enable_set) (struct spu *spu, u64 enable);
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u64 (*resource_allocation_enable_get) (struct spu *spu);
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};
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extern const struct spu_priv1_ops* spu_priv1_ops;
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static inline void
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spu_int_mask_and (struct spu *spu, int class, u64 mask)
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{
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spu_priv1_ops->int_mask_and(spu, class, mask);
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}
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static inline void
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spu_int_mask_or (struct spu *spu, int class, u64 mask)
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{
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spu_priv1_ops->int_mask_or(spu, class, mask);
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}
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static inline void
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spu_int_mask_set (struct spu *spu, int class, u64 mask)
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{
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spu_priv1_ops->int_mask_set(spu, class, mask);
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}
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static inline u64
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spu_int_mask_get (struct spu *spu, int class)
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{
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return spu_priv1_ops->int_mask_get(spu, class);
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}
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static inline void
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spu_int_stat_clear (struct spu *spu, int class, u64 stat)
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{
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spu_priv1_ops->int_stat_clear(spu, class, stat);
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}
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static inline u64
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spu_int_stat_get (struct spu *spu, int class)
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{
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return spu_priv1_ops->int_stat_get (spu, class);
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}
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static inline void
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spu_int_route_set (struct spu *spu, u64 route)
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{
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spu_priv1_ops->int_stat_get(spu, route);
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}
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static inline u64
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spu_mfc_dar_get (struct spu *spu)
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{
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return spu_priv1_ops->mfc_dar_get(spu);
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}
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static inline u64
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spu_mfc_dsisr_get (struct spu *spu)
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{
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return spu_priv1_ops->mfc_dsisr_get(spu);
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}
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static inline void
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spu_mfc_dsisr_set (struct spu *spu, u64 dsisr)
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{
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spu_priv1_ops->mfc_dsisr_set(spu, dsisr);
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}
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static inline void
|
||||
spu_mfc_sdr_set (struct spu *spu, u64 sdr)
|
||||
{
|
||||
spu_priv1_ops->mfc_sdr_set(spu, sdr);
|
||||
}
|
||||
|
||||
static inline void
|
||||
spu_mfc_sr1_set (struct spu *spu, u64 sr1)
|
||||
{
|
||||
spu_priv1_ops->mfc_sr1_set(spu, sr1);
|
||||
}
|
||||
|
||||
static inline u64
|
||||
spu_mfc_sr1_get (struct spu *spu)
|
||||
{
|
||||
return spu_priv1_ops->mfc_sr1_get(spu);
|
||||
}
|
||||
|
||||
static inline void
|
||||
spu_mfc_tclass_id_set (struct spu *spu, u64 tclass_id)
|
||||
{
|
||||
spu_priv1_ops->mfc_tclass_id_set(spu, tclass_id);
|
||||
}
|
||||
|
||||
static inline u64
|
||||
spu_mfc_tclass_id_get (struct spu *spu)
|
||||
{
|
||||
return spu_priv1_ops->mfc_tclass_id_get(spu);
|
||||
}
|
||||
|
||||
static inline void
|
||||
spu_tlb_invalidate (struct spu *spu)
|
||||
{
|
||||
spu_priv1_ops->tlb_invalidate(spu);
|
||||
}
|
||||
|
||||
static inline void
|
||||
spu_resource_allocation_groupID_set (struct spu *spu, u64 id)
|
||||
{
|
||||
spu_priv1_ops->resource_allocation_groupID_set(spu, id);
|
||||
}
|
||||
|
||||
static inline u64
|
||||
spu_resource_allocation_groupID_get (struct spu *spu)
|
||||
{
|
||||
return spu_priv1_ops->resource_allocation_groupID_get(spu);
|
||||
}
|
||||
|
||||
static inline void
|
||||
spu_resource_allocation_enable_set (struct spu *spu, u64 enable)
|
||||
{
|
||||
spu_priv1_ops->resource_allocation_enable_set(spu, enable);
|
||||
}
|
||||
|
||||
static inline u64
|
||||
spu_resource_allocation_enable_get (struct spu *spu)
|
||||
{
|
||||
return spu_priv1_ops->resource_allocation_enable_get(spu);
|
||||
}
|
||||
|
||||
/* The declarations folowing are put here for convenience
|
||||
* and only intended to be used by the platform setup code
|
||||
* for initializing spu_priv1_ops.
|
||||
*/
|
||||
|
||||
extern const struct spu_priv1_ops spu_priv1_mmio_ops;
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
#endif
|
||||
Loading…
Reference in New Issue