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drm/i915: Update ring->dispatch_execbuffer() to take a request structure 

Updated the various ring->dispatch_execbuffer() implementations to take a
request instead of a ring.

For: VIZ-5115
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Tomas Elf <tomas.elf@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
John Harrison 2015-05-29 17:44:02 +01:00 committed by Daniel Vetter
parent c4e766389e
commit 53fddaf70d
4 changed files with 16 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/i915/i915_gem_execbuffer.c
View File

@ -1328,14 +1328,14 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
if (ret)
goto error;
ret = ring->dispatch_execbuffer(ring,
ret = ring->dispatch_execbuffer(params->request,
exec_start, exec_len,
params->dispatch_flags);
if (ret)
goto error;
}
} else {
ret = ring->dispatch_execbuffer(ring,
ret = ring->dispatch_execbuffer(params->request,
exec_start, exec_len,
params->dispatch_flags);
if (ret)

3
drivers/gpu/drm/i915/i915_gem_render_state.c
View File

@ -164,8 +164,7 @@ int i915_gem_render_state_init(struct drm_i915_gem_request *req)
if (so.rodata == NULL)
return 0;
ret = req->ring->dispatch_execbuffer(req->ring,
so.ggtt_offset,
ret = req->ring->dispatch_execbuffer(req, so.ggtt_offset,
so.rodata->batch_items * 4,
I915_DISPATCH_SECURE);
if (ret)

18
drivers/gpu/drm/i915/intel_ringbuffer.c
View File

@ -1760,10 +1760,11 @@ gen8_ring_put_irq(struct intel_engine_cs *ring)
}
static int
i965_dispatch_execbuffer(struct intel_engine_cs *ring,
i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 length,
unsigned dispatch_flags)
{
struct intel_engine_cs *ring = req->ring;
int ret;
ret = intel_ring_begin(ring, 2);
@ -1786,10 +1787,11 @@ i965_dispatch_execbuffer(struct intel_engine_cs *ring,
#define I830_TLB_ENTRIES (2)
#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
static int
i830_dispatch_execbuffer(struct intel_engine_cs *ring,
i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
struct intel_engine_cs *ring = req->ring;
u32 cs_offset = ring->scratch.gtt_offset;
int ret;
@ -1848,10 +1850,11 @@ i830_dispatch_execbuffer(struct intel_engine_cs *ring,
}
static int
i915_dispatch_execbuffer(struct intel_engine_cs *ring,
i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
struct intel_engine_cs *ring = req->ring;
int ret;
ret = intel_ring_begin(ring, 2);
@ -2423,10 +2426,11 @@ static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
}
static int
gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
struct intel_engine_cs *ring = req->ring;
bool ppgtt = USES_PPGTT(ring->dev) &&
!(dispatch_flags & I915_DISPATCH_SECURE);
int ret;
@ -2446,10 +2450,11 @@ gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
}
static int
hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
struct intel_engine_cs *ring = req->ring;
int ret;
ret = intel_ring_begin(ring, 2);
@ -2468,10 +2473,11 @@ hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
}
static int
gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
struct intel_engine_cs *ring = req->ring;
int ret;
ret = intel_ring_begin(ring, 2);

2
drivers/gpu/drm/i915/intel_ringbuffer.h
View File

@ -194,7 +194,7 @@ struct intel_engine_cs {
bool lazy_coherency);
void (*set_seqno)(struct intel_engine_cs *ring,
u32 seqno);
int (*dispatch_execbuffer)(struct intel_engine_cs *ring,
int (*dispatch_execbuffer)(struct drm_i915_gem_request *req,
u64 offset, u32 length,
unsigned dispatch_flags);
#define I915_DISPATCH_SECURE 0x1