staging: mt7621-pci-phy: remove driver from staging
Remove this driver from staging because it has been moved into its properly place in the kernel. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Link: https://lore.kernel.org/r/20201121155037.21354-5-sergio.paracuellos@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Sergio Paracuellos
Vinod Koul
parent
370c10afc1
commit
53e7c92c7f
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@ -94,8 +94,6 @@ source "drivers/staging/pi433/Kconfig"
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source "drivers/staging/mt7621-pci/Kconfig"
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source "drivers/staging/mt7621-pci/Kconfig"
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source "drivers/staging/mt7621-pci-phy/Kconfig"
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source "drivers/staging/mt7621-pinctrl/Kconfig"
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source "drivers/staging/mt7621-pinctrl/Kconfig"
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source "drivers/staging/mt7621-dma/Kconfig"
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source "drivers/staging/mt7621-dma/Kconfig"
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@ -37,7 +37,6 @@ obj-$(CONFIG_GREYBUS) += greybus/
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obj-$(CONFIG_BCM2835_VCHIQ) += vc04_services/
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obj-$(CONFIG_BCM2835_VCHIQ) += vc04_services/
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obj-$(CONFIG_PI433) += pi433/
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obj-$(CONFIG_PI433) += pi433/
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obj-$(CONFIG_PCI_MT7621) += mt7621-pci/
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obj-$(CONFIG_PCI_MT7621) += mt7621-pci/
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obj-$(CONFIG_PCI_MT7621_PHY) += mt7621-pci-phy/
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obj-$(CONFIG_PINCTRL_RT2880) += mt7621-pinctrl/
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obj-$(CONFIG_PINCTRL_RT2880) += mt7621-pinctrl/
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obj-$(CONFIG_SOC_MT7621) += mt7621-dma/
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obj-$(CONFIG_SOC_MT7621) += mt7621-dma/
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obj-$(CONFIG_DMA_RALINK) += ralink-gdma/
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obj-$(CONFIG_DMA_RALINK) += ralink-gdma/
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@ -1,8 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0
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config PCI_MT7621_PHY
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tristate "MediaTek MT7621 PCI PHY Driver"
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depends on RALINK && OF
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select GENERIC_PHY
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help
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Say 'Y' here to add support for MediaTek MT7621 PCI PHY driver,
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@ -1,2 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_PCI_MT7621_PHY) += pci-mt7621-phy.o
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@ -1,4 +0,0 @@
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- general code review and cleanup
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Cc: NeilBrown <neil@brown.name> and Sergio Paracuellos <sergio.paracuellos@gmail.com>
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@ -1,36 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/phy/mediatek,mt7621-pci-phy.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Mediatek Mt7621 PCIe PHY Device Tree Bindings
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maintainers:
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- Sergio Paracuellos <sergio.paracuellos@gmail.com>
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properties:
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compatible:
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const: mediatek,mt7621-pci-phy
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reg:
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maxItems: 1
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"#phy-cells":
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const: 1
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description: selects if the phy is dual-ported
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required:
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- compatible
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- reg
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- "#phy-cells"
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additionalProperties: false
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examples:
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- |
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pcie0_phy: pcie-phy@1e149000 {
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compatible = "mediatek,mt7621-pci-phy";
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reg = <0x1e149000 0x0700>;
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#phy-cells = <1>;
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};
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@ -1,373 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Mediatek MT7621 PCI PHY Driver
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* Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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*/
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#include <dt-bindings/phy/phy.h>
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#include <linux/bitops.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/sys_soc.h>
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#include <mt7621.h>
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#include <ralink_regs.h>
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#define RG_PE1_PIPE_REG 0x02c
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#define RG_PE1_PIPE_RST BIT(12)
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#define RG_PE1_PIPE_CMD_FRC BIT(4)
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#define RG_P0_TO_P1_WIDTH 0x100
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#define RG_PE1_H_LCDDS_REG 0x49c
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#define RG_PE1_H_LCDDS_PCW GENMASK(30, 0)
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#define RG_PE1_H_LCDDS_PCW_VAL(x) ((0x7fffffff & (x)) << 0)
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#define RG_PE1_FRC_H_XTAL_REG 0x400
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#define RG_PE1_FRC_H_XTAL_TYPE BIT(8)
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#define RG_PE1_H_XTAL_TYPE GENMASK(10, 9)
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#define RG_PE1_H_XTAL_TYPE_VAL(x) ((0x3 & (x)) << 9)
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#define RG_PE1_FRC_PHY_REG 0x000
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#define RG_PE1_FRC_PHY_EN BIT(4)
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#define RG_PE1_PHY_EN BIT(5)
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#define RG_PE1_H_PLL_REG 0x490
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#define RG_PE1_H_PLL_BC GENMASK(23, 22)
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#define RG_PE1_H_PLL_BC_VAL(x) ((0x3 & (x)) << 22)
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#define RG_PE1_H_PLL_BP GENMASK(21, 18)
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#define RG_PE1_H_PLL_BP_VAL(x) ((0xf & (x)) << 18)
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#define RG_PE1_H_PLL_IR GENMASK(15, 12)
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#define RG_PE1_H_PLL_IR_VAL(x) ((0xf & (x)) << 12)
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#define RG_PE1_H_PLL_IC GENMASK(11, 8)
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#define RG_PE1_H_PLL_IC_VAL(x) ((0xf & (x)) << 8)
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#define RG_PE1_H_PLL_PREDIV GENMASK(7, 6)
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#define RG_PE1_H_PLL_PREDIV_VAL(x) ((0x3 & (x)) << 6)
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#define RG_PE1_PLL_DIVEN GENMASK(3, 1)
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#define RG_PE1_PLL_DIVEN_VAL(x) ((0x7 & (x)) << 1)
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#define RG_PE1_H_PLL_FBKSEL_REG 0x4bc
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#define RG_PE1_H_PLL_FBKSEL GENMASK(5, 4)
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#define RG_PE1_H_PLL_FBKSEL_VAL(x) ((0x3 & (x)) << 4)
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#define RG_PE1_H_LCDDS_SSC_PRD_REG 0x4a4
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#define RG_PE1_H_LCDDS_SSC_PRD GENMASK(15, 0)
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#define RG_PE1_H_LCDDS_SSC_PRD_VAL(x) ((0xffff & (x)) << 0)
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#define RG_PE1_H_LCDDS_SSC_DELTA_REG 0x4a8
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#define RG_PE1_H_LCDDS_SSC_DELTA GENMASK(11, 0)
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#define RG_PE1_H_LCDDS_SSC_DELTA_VAL(x) ((0xfff & (x)) << 0)
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#define RG_PE1_H_LCDDS_SSC_DELTA1 GENMASK(27, 16)
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#define RG_PE1_H_LCDDS_SSC_DELTA1_VAL(x) ((0xff & (x)) << 16)
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#define RG_PE1_LCDDS_CLK_PH_INV_REG 0x4a0
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#define RG_PE1_LCDDS_CLK_PH_INV BIT(5)
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#define RG_PE1_H_PLL_BR_REG 0x4ac
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#define RG_PE1_H_PLL_BR GENMASK(18, 16)
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#define RG_PE1_H_PLL_BR_VAL(x) ((0x7 & (x)) << 16)
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#define RG_PE1_MSTCKDIV_REG 0x414
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#define RG_PE1_MSTCKDIV GENMASK(7, 6)
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#define RG_PE1_MSTCKDIV_VAL(x) ((0x3 & (x)) << 6)
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#define RG_PE1_FRC_MSTCKDIV BIT(5)
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#define XTAL_MODE_SEL_SHIFT 6
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#define XTAL_MODE_SEL_MASK 0x7
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#define MAX_PHYS 2
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/**
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* struct mt7621_pci_phy - Mt7621 Pcie PHY core
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* @dev: pointer to device
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* @regmap: kernel regmap pointer
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* @phy: pointer to the kernel PHY device
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* @port_base: base register
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* @has_dual_port: if the phy has dual ports.
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* @bypass_pipe_rst: mark if 'mt7621_bypass_pipe_rst'
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* needs to be executed. Depends on chip revision.
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*/
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struct mt7621_pci_phy {
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struct device *dev;
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struct regmap *regmap;
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struct phy *phy;
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void __iomem *port_base;
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bool has_dual_port;
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bool bypass_pipe_rst;
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};
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static inline u32 phy_read(struct mt7621_pci_phy *phy, u32 reg)
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{
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u32 val;
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regmap_read(phy->regmap, reg, &val);
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return val;
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}
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static inline void phy_write(struct mt7621_pci_phy *phy, u32 val, u32 reg)
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{
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regmap_write(phy->regmap, reg, val);
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}
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static inline void mt7621_phy_rmw(struct mt7621_pci_phy *phy,
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u32 reg, u32 clr, u32 set)
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{
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u32 val = phy_read(phy, reg);
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val &= ~clr;
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val |= set;
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phy_write(phy, val, reg);
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}
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static void mt7621_bypass_pipe_rst(struct mt7621_pci_phy *phy)
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{
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mt7621_phy_rmw(phy, RG_PE1_PIPE_REG, 0, RG_PE1_PIPE_RST);
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mt7621_phy_rmw(phy, RG_PE1_PIPE_REG, 0, RG_PE1_PIPE_CMD_FRC);
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if (phy->has_dual_port) {
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mt7621_phy_rmw(phy, RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH,
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0, RG_PE1_PIPE_RST);
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mt7621_phy_rmw(phy, RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH,
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0, RG_PE1_PIPE_CMD_FRC);
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}
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}
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static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy)
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{
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struct device *dev = phy->dev;
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u32 xtal_mode;
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xtal_mode = (rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0)
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>> XTAL_MODE_SEL_SHIFT) & XTAL_MODE_SEL_MASK;
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/* Set PCIe Port PHY to disable SSC */
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/* Debug Xtal Type */
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mt7621_phy_rmw(phy, RG_PE1_FRC_H_XTAL_REG,
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RG_PE1_FRC_H_XTAL_TYPE | RG_PE1_H_XTAL_TYPE,
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RG_PE1_FRC_H_XTAL_TYPE | RG_PE1_H_XTAL_TYPE_VAL(0x00));
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/* disable port */
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mt7621_phy_rmw(phy, RG_PE1_FRC_PHY_REG,
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RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
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if (phy->has_dual_port) {
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mt7621_phy_rmw(phy, RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH,
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RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
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}
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if (xtal_mode <= 5 && xtal_mode >= 3) { /* 40MHz Xtal */
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/* Set Pre-divider ratio (for host mode) */
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mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG,
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RG_PE1_H_PLL_PREDIV,
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RG_PE1_H_PLL_PREDIV_VAL(0x01));
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dev_info(dev, "Xtal is 40MHz\n");
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} else if (xtal_mode >= 6) { /* 25MHz Xal */
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mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG,
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RG_PE1_H_PLL_PREDIV,
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RG_PE1_H_PLL_PREDIV_VAL(0x00));
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/* Select feedback clock */
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mt7621_phy_rmw(phy, RG_PE1_H_PLL_FBKSEL_REG,
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RG_PE1_H_PLL_FBKSEL,
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RG_PE1_H_PLL_FBKSEL_VAL(0x01));
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/* DDS NCPO PCW (for host mode) */
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mt7621_phy_rmw(phy, RG_PE1_H_LCDDS_SSC_PRD_REG,
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RG_PE1_H_LCDDS_SSC_PRD,
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RG_PE1_H_LCDDS_SSC_PRD_VAL(0x18000000));
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/* DDS SSC dither period control */
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mt7621_phy_rmw(phy, RG_PE1_H_LCDDS_SSC_PRD_REG,
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RG_PE1_H_LCDDS_SSC_PRD,
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RG_PE1_H_LCDDS_SSC_PRD_VAL(0x18d));
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/* DDS SSC dither amplitude control */
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mt7621_phy_rmw(phy, RG_PE1_H_LCDDS_SSC_DELTA_REG,
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RG_PE1_H_LCDDS_SSC_DELTA |
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RG_PE1_H_LCDDS_SSC_DELTA1,
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RG_PE1_H_LCDDS_SSC_DELTA_VAL(0x4a) |
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RG_PE1_H_LCDDS_SSC_DELTA1_VAL(0x4a));
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dev_info(dev, "Xtal is 25MHz\n");
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} else { /* 20MHz Xtal */
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mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG,
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RG_PE1_H_PLL_PREDIV,
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RG_PE1_H_PLL_PREDIV_VAL(0x00));
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dev_info(dev, "Xtal is 20MHz\n");
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}
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/* DDS clock inversion */
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mt7621_phy_rmw(phy, RG_PE1_LCDDS_CLK_PH_INV_REG,
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RG_PE1_LCDDS_CLK_PH_INV, RG_PE1_LCDDS_CLK_PH_INV);
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/* Set PLL bits */
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mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG,
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RG_PE1_H_PLL_BC | RG_PE1_H_PLL_BP | RG_PE1_H_PLL_IR |
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RG_PE1_H_PLL_IC | RG_PE1_PLL_DIVEN,
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RG_PE1_H_PLL_BC_VAL(0x02) | RG_PE1_H_PLL_BP_VAL(0x06) |
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RG_PE1_H_PLL_IR_VAL(0x02) | RG_PE1_H_PLL_IC_VAL(0x01) |
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RG_PE1_PLL_DIVEN_VAL(0x02));
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mt7621_phy_rmw(phy, RG_PE1_H_PLL_BR_REG,
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RG_PE1_H_PLL_BR, RG_PE1_H_PLL_BR_VAL(0x00));
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if (xtal_mode <= 5 && xtal_mode >= 3) { /* 40MHz Xtal */
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/* set force mode enable of da_pe1_mstckdiv */
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mt7621_phy_rmw(phy, RG_PE1_MSTCKDIV_REG,
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RG_PE1_MSTCKDIV | RG_PE1_FRC_MSTCKDIV,
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RG_PE1_MSTCKDIV_VAL(0x01) | RG_PE1_FRC_MSTCKDIV);
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}
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}
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static int mt7621_pci_phy_init(struct phy *phy)
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{
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struct mt7621_pci_phy *mphy = phy_get_drvdata(phy);
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if (mphy->bypass_pipe_rst)
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mt7621_bypass_pipe_rst(mphy);
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mt7621_set_phy_for_ssc(mphy);
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return 0;
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}
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static int mt7621_pci_phy_power_on(struct phy *phy)
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{
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|
||||||
struct mt7621_pci_phy *mphy = phy_get_drvdata(phy);
|
|
||||||
|
|
||||||
/* Enable PHY and disable force mode */
|
|
||||||
mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG,
|
|
||||||
RG_PE1_FRC_PHY_EN, RG_PE1_PHY_EN);
|
|
||||||
|
|
||||||
if (mphy->has_dual_port) {
|
|
||||||
mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH,
|
|
||||||
RG_PE1_FRC_PHY_EN, RG_PE1_PHY_EN);
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int mt7621_pci_phy_power_off(struct phy *phy)
|
|
||||||
{
|
|
||||||
struct mt7621_pci_phy *mphy = phy_get_drvdata(phy);
|
|
||||||
|
|
||||||
/* Disable PHY */
|
|
||||||
mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG,
|
|
||||||
RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
|
|
||||||
|
|
||||||
if (mphy->has_dual_port) {
|
|
||||||
mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH,
|
|
||||||
RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int mt7621_pci_phy_exit(struct phy *phy)
|
|
||||||
{
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static const struct phy_ops mt7621_pci_phy_ops = {
|
|
||||||
.init = mt7621_pci_phy_init,
|
|
||||||
.exit = mt7621_pci_phy_exit,
|
|
||||||
.power_on = mt7621_pci_phy_power_on,
|
|
||||||
.power_off = mt7621_pci_phy_power_off,
|
|
||||||
.owner = THIS_MODULE,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct phy *mt7621_pcie_phy_of_xlate(struct device *dev,
|
|
||||||
struct of_phandle_args *args)
|
|
||||||
{
|
|
||||||
struct mt7621_pci_phy *mt7621_phy = dev_get_drvdata(dev);
|
|
||||||
|
|
||||||
if (WARN_ON(args->args[0] >= MAX_PHYS))
|
|
||||||
return ERR_PTR(-ENODEV);
|
|
||||||
|
|
||||||
mt7621_phy->has_dual_port = args->args[0];
|
|
||||||
|
|
||||||
dev_info(dev, "PHY for 0x%08x (dual port = %d)\n",
|
|
||||||
(unsigned int)mt7621_phy->port_base, mt7621_phy->has_dual_port);
|
|
||||||
|
|
||||||
return mt7621_phy->phy;
|
|
||||||
}
|
|
||||||
|
|
||||||
static const struct soc_device_attribute mt7621_pci_quirks_match[] = {
|
|
||||||
{ .soc_id = "mt7621", .revision = "E2" }
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct regmap_config mt7621_pci_phy_regmap_config = {
|
|
||||||
.reg_bits = 32,
|
|
||||||
.val_bits = 32,
|
|
||||||
.reg_stride = 4,
|
|
||||||
.max_register = 0x700,
|
|
||||||
};
|
|
||||||
|
|
||||||
static int mt7621_pci_phy_probe(struct platform_device *pdev)
|
|
||||||
{
|
|
||||||
struct device *dev = &pdev->dev;
|
|
||||||
const struct soc_device_attribute *attr;
|
|
||||||
struct phy_provider *provider;
|
|
||||||
struct mt7621_pci_phy *phy;
|
|
||||||
struct resource *res;
|
|
||||||
|
|
||||||
phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
|
|
||||||
if (!phy)
|
|
||||||
return -ENOMEM;
|
|
||||||
|
|
||||||
attr = soc_device_match(mt7621_pci_quirks_match);
|
|
||||||
if (attr)
|
|
||||||
phy->bypass_pipe_rst = true;
|
|
||||||
|
|
||||||
phy->dev = dev;
|
|
||||||
platform_set_drvdata(pdev, phy);
|
|
||||||
|
|
||||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
||||||
if (!res) {
|
|
||||||
dev_err(dev, "failed to get address resource\n");
|
|
||||||
return -ENXIO;
|
|
||||||
}
|
|
||||||
|
|
||||||
phy->port_base = devm_ioremap_resource(dev, res);
|
|
||||||
if (IS_ERR(phy->port_base)) {
|
|
||||||
dev_err(dev, "failed to remap phy regs\n");
|
|
||||||
return PTR_ERR(phy->port_base);
|
|
||||||
}
|
|
||||||
|
|
||||||
phy->regmap = devm_regmap_init_mmio(phy->dev, phy->port_base,
|
|
||||||
&mt7621_pci_phy_regmap_config);
|
|
||||||
if (IS_ERR(phy->regmap))
|
|
||||||
return PTR_ERR(phy->regmap);
|
|
||||||
|
|
||||||
phy->phy = devm_phy_create(dev, dev->of_node, &mt7621_pci_phy_ops);
|
|
||||||
if (IS_ERR(phy)) {
|
|
||||||
dev_err(dev, "failed to create phy\n");
|
|
||||||
return PTR_ERR(phy);
|
|
||||||
}
|
|
||||||
|
|
||||||
phy_set_drvdata(phy->phy, phy);
|
|
||||||
|
|
||||||
provider = devm_of_phy_provider_register(dev, mt7621_pcie_phy_of_xlate);
|
|
||||||
|
|
||||||
return PTR_ERR_OR_ZERO(provider);
|
|
||||||
}
|
|
||||||
|
|
||||||
static const struct of_device_id mt7621_pci_phy_ids[] = {
|
|
||||||
{ .compatible = "mediatek,mt7621-pci-phy" },
|
|
||||||
{},
|
|
||||||
};
|
|
||||||
MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
|
|
||||||
|
|
||||||
static struct platform_driver mt7621_pci_phy_driver = {
|
|
||||||
.probe = mt7621_pci_phy_probe,
|
|
||||||
.driver = {
|
|
||||||
.name = "mt7621-pci-phy",
|
|
||||||
.of_match_table = of_match_ptr(mt7621_pci_phy_ids),
|
|
||||||
},
|
|
||||||
};
|
|
||||||
|
|
||||||
builtin_platform_driver(mt7621_pci_phy_driver);
|
|
||||||
|
|
||||||
MODULE_AUTHOR("Sergio Paracuellos <sergio.paracuellos@gmail.com>");
|
|
||||||
MODULE_DESCRIPTION("MediaTek MT7621 PCIe PHY driver");
|
|
||||||
MODULE_LICENSE("GPL v2");
|
|
||||||
Loading…
Reference in New Issue