staging: xillybus: Register's address offset notation update
In iowrite32() calls, the address of registers was expressed as e.g. &ep->registers[fpga_msg_ctrl_reg]. This changes to the more common format e.g. ep->registers + fpga_msg_ctrl_reg. There is no functional change. Signed-off-by: Eli Billauer <eli.billauer@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Eli Billauer
Greg Kroah-Hartman
parent
049c1fb4fc
commit
539889ee49
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@ -99,7 +99,7 @@ struct xilly_endpoint {
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struct list_head ep_list;
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int dma_using_dac; /* =1 if 64-bit DMA is used, =0 otherwise. */
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__iomem u32 *registers;
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__iomem void *registers;
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int fatal_error;
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struct mutex register_mutex;
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@ -44,14 +44,14 @@ MODULE_LICENSE("GPL v2");
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#define XILLY_RX_TIMEOUT (10*HZ/1000)
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#define XILLY_TIMEOUT (100*HZ/1000)
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#define fpga_msg_ctrl_reg 0x0002
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#define fpga_dma_control_reg 0x0008
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#define fpga_dma_bufno_reg 0x0009
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#define fpga_dma_bufaddr_lowaddr_reg 0x000a
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#define fpga_dma_bufaddr_highaddr_reg 0x000b
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#define fpga_buf_ctrl_reg 0x000c
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#define fpga_buf_offset_reg 0x000d
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#define fpga_endian_reg 0x0010
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#define fpga_msg_ctrl_reg 0x0008
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#define fpga_dma_control_reg 0x0020
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#define fpga_dma_bufno_reg 0x0024
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#define fpga_dma_bufaddr_lowaddr_reg 0x0028
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#define fpga_dma_bufaddr_highaddr_reg 0x002c
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#define fpga_buf_ctrl_reg 0x0030
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#define fpga_buf_offset_reg 0x0034
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#define fpga_endian_reg 0x0040
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#define XILLYMSG_OPCODE_RELEASEBUF 1
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#define XILLYMSG_OPCODE_QUIESCEACK 2
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@ -170,7 +170,7 @@ irqreturn_t xillybus_isr(int irq, void *data)
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DMA_FROM_DEVICE);
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iowrite32(0x01, /* Message NACK */
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&ep->registers[fpga_msg_ctrl_reg]);
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ep->registers + fpga_msg_ctrl_reg);
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}
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return IRQ_HANDLED;
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} else if (buf[i] & (1 << 22)) /* Last message */
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@ -305,7 +305,7 @@ irqreturn_t xillybus_isr(int irq, void *data)
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ep->msg_counter = (ep->msg_counter + 1) & 0xf;
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ep->failed_messages = 0;
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iowrite32(0x03, &ep->registers[fpga_msg_ctrl_reg]); /* Message ACK */
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iowrite32(0x03, ep->registers + fpga_msg_ctrl_reg); /* Message ACK */
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return IRQ_HANDLED;
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}
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@ -387,9 +387,9 @@ static int xilly_get_dma_buffers(struct xilly_endpoint *ep,
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return rc;
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iowrite32((u32) (dma_addr & 0xffffffff),
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&ep->registers[fpga_dma_bufaddr_lowaddr_reg]);
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ep->registers + fpga_dma_bufaddr_lowaddr_reg);
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iowrite32(((u32) ((((u64) dma_addr) >> 32) & 0xffffffff)),
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&ep->registers[fpga_dma_bufaddr_highaddr_reg]);
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ep->registers + fpga_dma_bufaddr_highaddr_reg);
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mmiowb();
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if (buffers) { /* Not the message buffer */
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@ -398,14 +398,14 @@ static int xilly_get_dma_buffers(struct xilly_endpoint *ep,
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buffers[i] = this_buffer++;
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iowrite32(s->regdirection | s->nbuffer++,
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&ep->registers[fpga_dma_bufno_reg]);
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ep->registers + fpga_dma_bufno_reg);
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} else {
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ep->msgbuf_addr = s->salami;
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ep->msgbuf_dma_addr = dma_addr;
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ep->msg_buf_size = bytebufsize;
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iowrite32(s->regdirection,
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&ep->registers[fpga_dma_bufno_reg]);
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ep->registers + fpga_dma_bufno_reg);
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}
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s->left_of_salami -= bytebufsize;
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@ -640,7 +640,7 @@ static int xilly_obtain_idt(struct xilly_endpoint *endpoint)
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iowrite32(1 |
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(3 << 24), /* Opcode 3 for channel 0 = Send IDT */
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&endpoint->registers[fpga_buf_ctrl_reg]);
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endpoint->registers + fpga_buf_ctrl_reg);
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mmiowb(); /* Just to appear safe */
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wait_event_interruptible_timeout(channel->wr_wait,
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@ -812,8 +812,8 @@ static ssize_t xillybus_read(struct file *filp, char __user *userbuf,
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iowrite32(1 | (channel->chan_num << 1)
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| (bufidx << 12),
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&channel->endpoint->registers[
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fpga_buf_ctrl_reg]);
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channel->endpoint->registers +
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fpga_buf_ctrl_reg);
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mmiowb(); /* Just to appear safe */
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}
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@ -899,15 +899,15 @@ static ssize_t xillybus_read(struct file *filp, char __user *userbuf,
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mutex_lock(&channel->endpoint->register_mutex);
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iowrite32(offsetlimit,
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&channel->endpoint->registers[
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fpga_buf_offset_reg]);
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channel->endpoint->registers +
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fpga_buf_offset_reg);
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mmiowb();
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iowrite32(1 | (channel->chan_num << 1) |
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(2 << 24) | /* 2 = offset limit */
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(waiting_bufidx << 12),
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&channel->endpoint->registers[
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fpga_buf_ctrl_reg]);
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channel->endpoint->registers +
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fpga_buf_ctrl_reg);
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mmiowb(); /* Just to appear safe */
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@ -999,8 +999,8 @@ desperate:
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iowrite32(1 | (channel->chan_num << 1) |
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(3 << 24) | /* Opcode 3, flush it all! */
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(waiting_bufidx << 12),
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&channel->endpoint->registers[
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fpga_buf_ctrl_reg]);
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channel->endpoint->registers +
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fpga_buf_ctrl_reg);
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mmiowb(); /* Just to appear safe */
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}
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@ -1112,13 +1112,13 @@ static int xillybus_myflush(struct xilly_channel *channel, long timeout)
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mutex_lock(&channel->endpoint->register_mutex);
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iowrite32(end_offset_plus1 - 1,
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&channel->endpoint->registers[fpga_buf_offset_reg]);
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channel->endpoint->registers + fpga_buf_offset_reg);
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mmiowb();
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iowrite32((channel->chan_num << 1) | /* Channel ID */
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(2 << 24) | /* Opcode 2, submit buffer */
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(bufidx << 12),
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&channel->endpoint->registers[fpga_buf_ctrl_reg]);
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channel->endpoint->registers + fpga_buf_ctrl_reg);
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mmiowb(); /* Just to appear safe */
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mutex_unlock(&channel->endpoint->register_mutex);
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@ -1362,14 +1362,14 @@ static ssize_t xillybus_write(struct file *filp, const char __user *userbuf,
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mutex_lock(&channel->endpoint->register_mutex);
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iowrite32(end_offset_plus1 - 1,
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&channel->endpoint->registers[
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fpga_buf_offset_reg]);
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channel->endpoint->registers +
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fpga_buf_offset_reg);
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mmiowb();
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iowrite32((channel->chan_num << 1) |
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(2 << 24) | /* 2 = submit buffer */
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(bufidx << 12),
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&channel->endpoint->registers[
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fpga_buf_ctrl_reg]);
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channel->endpoint->registers +
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fpga_buf_ctrl_reg);
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mmiowb(); /* Just to appear safe */
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mutex_unlock(&channel->endpoint->
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@ -1564,8 +1564,8 @@ static int xillybus_open(struct inode *inode, struct file *filp)
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iowrite32(1 | (channel->chan_num << 1) |
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(4 << 24) | /* Opcode 4, open channel */
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((channel->wr_synchronous & 1) << 23),
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&channel->endpoint->registers[
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fpga_buf_ctrl_reg]);
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channel->endpoint->registers +
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fpga_buf_ctrl_reg);
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mmiowb(); /* Just to appear safe */
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}
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@ -1586,8 +1586,8 @@ static int xillybus_open(struct inode *inode, struct file *filp)
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iowrite32((channel->chan_num << 1) |
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(4 << 24), /* Opcode 4, open channel */
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&channel->endpoint->registers[
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fpga_buf_ctrl_reg]);
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channel->endpoint->registers +
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fpga_buf_ctrl_reg);
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mmiowb(); /* Just to appear safe */
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}
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@ -1639,8 +1639,8 @@ static int xillybus_release(struct inode *inode, struct file *filp)
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iowrite32((channel->chan_num << 1) | /* Channel ID */
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(5 << 24), /* Opcode 5, close channel */
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&channel->endpoint->registers[
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fpga_buf_ctrl_reg]);
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channel->endpoint->registers +
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fpga_buf_ctrl_reg);
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mmiowb(); /* Just to appear safe */
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}
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mutex_unlock(&channel->rd_mutex);
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@ -1660,8 +1660,8 @@ static int xillybus_release(struct inode *inode, struct file *filp)
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iowrite32(1 | (channel->chan_num << 1) |
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(5 << 24), /* Opcode 5, close channel */
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&channel->endpoint->registers[
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fpga_buf_ctrl_reg]);
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channel->endpoint->registers +
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fpga_buf_ctrl_reg);
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mmiowb(); /* Just to appear safe */
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/*
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@ -1766,11 +1766,11 @@ static loff_t xillybus_llseek(struct file *filp, loff_t offset, int whence)
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mutex_lock(&channel->endpoint->register_mutex);
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iowrite32(pos >> channel->log2_element_size,
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&channel->endpoint->registers[fpga_buf_offset_reg]);
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channel->endpoint->registers + fpga_buf_offset_reg);
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mmiowb();
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iowrite32((channel->chan_num << 1) |
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(6 << 24), /* Opcode 6, set address */
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&channel->endpoint->registers[fpga_buf_ctrl_reg]);
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channel->endpoint->registers + fpga_buf_ctrl_reg);
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mmiowb(); /* Just to appear safe */
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mutex_unlock(&channel->endpoint->register_mutex);
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@ -1987,7 +1987,7 @@ static int xilly_quiesce(struct xilly_endpoint *endpoint)
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endpoint->idtlen = -1;
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wmb(); /* Make sure idtlen is set before sending command */
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iowrite32((u32) (endpoint->dma_using_dac & 0x0001),
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&endpoint->registers[fpga_dma_control_reg]);
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endpoint->registers + fpga_dma_control_reg);
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mmiowb();
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wait_event_interruptible_timeout(endpoint->ep_wait,
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@ -2027,7 +2027,7 @@ int xillybus_endpoint_discovery(struct xilly_endpoint *endpoint)
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* necessary.
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*/
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iowrite32(1, &endpoint->registers[fpga_endian_reg]);
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iowrite32(1, endpoint->registers + fpga_endian_reg);
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mmiowb(); /* Writes below are affected by the one above. */
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/* Bootstrap phase I: Allocate temporary message buffer */
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@ -2044,7 +2044,7 @@ int xillybus_endpoint_discovery(struct xilly_endpoint *endpoint)
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return rc;
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/* Clear the message subsystem (and counter in particular) */
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iowrite32(0x04, &endpoint->registers[fpga_msg_ctrl_reg]);
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iowrite32(0x04, endpoint->registers + fpga_msg_ctrl_reg);
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mmiowb();
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endpoint->idtlen = -1;
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@ -2056,7 +2056,7 @@ int xillybus_endpoint_discovery(struct xilly_endpoint *endpoint)
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* buffer size.
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*/
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iowrite32((u32) (endpoint->dma_using_dac & 0x0001),
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&endpoint->registers[fpga_dma_control_reg]);
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endpoint->registers + fpga_dma_control_reg);
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mmiowb();
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wait_event_interruptible_timeout(endpoint->ep_wait,
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@ -2070,7 +2070,7 @@ int xillybus_endpoint_discovery(struct xilly_endpoint *endpoint)
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/* Enable DMA */
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iowrite32((u32) (0x0002 | (endpoint->dma_using_dac & 0x0001)),
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&endpoint->registers[fpga_dma_control_reg]);
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endpoint->registers + fpga_dma_control_reg);
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mmiowb();
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/* Bootstrap phase II: Allocate buffer for IDT and obtain it */
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