clk: socfpga: remove clk_ops enable/disable methods
The enable/disable clock ops are already defined in the standard clock ops, so we don't need to assign them. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lkml.kernel.org/r/20200512181647.5071-2-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -102,8 +102,6 @@ static struct clk * __init __socfpga_pll_init(struct device_node *node,
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pll_clk->hw.hw.init = &init;
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pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
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clk_pll_ops.enable = clk_gate_ops.enable;
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clk_pll_ops.disable = clk_gate_ops.disable;
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clk = clk_register(NULL, &pll_clk->hw.hw);
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if (WARN_ON(IS_ERR(clk))) {
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@ -138,8 +138,6 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *clks,
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pll_clk->hw.hw.init = &init;
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pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
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clk_pll_ops.enable = clk_gate_ops.enable;
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clk_pll_ops.disable = clk_gate_ops.disable;
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clk = clk_register(NULL, &pll_clk->hw.hw);
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if (WARN_ON(IS_ERR(clk))) {
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@ -105,8 +105,6 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node,
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pll_clk->hw.hw.init = &init;
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pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
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clk_pll_ops.enable = clk_gate_ops.enable;
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clk_pll_ops.disable = clk_gate_ops.disable;
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clk = clk_register(NULL, &pll_clk->hw.hw);
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if (WARN_ON(IS_ERR(clk))) {
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