memory: mtk-smi: Adjust some code position
No functional change. Only move the code position to make the code more readable. 1. Put the register smi-common above smi-larb. Prepare to add some others register setting. 2. Put mtk_smi_larb_unbind around larb_bind. 3. Sort the SoC data alphabetically. and put them in one line as the current kernel allow it. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: Ikjoon Jang <ikjn@chromium.org> Link: https://lore.kernel.org/r/20210914113703.31466-6-yong.wu@mediatek.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
This commit is contained in:
Yong Wu
Krzysztof Kozlowski
parent
a5c18986f4
commit
534e0ad2ed
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@ -17,13 +17,16 @@
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#include <dt-bindings/memory/mt2701-larb-port.h>
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#include <dt-bindings/memory/mtk-memory-port.h>
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/* mt8173 */
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#define SMI_LARB_MMU_EN 0xf00
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/* SMI COMMON */
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#define SMI_BUS_SEL 0x220
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#define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1)
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/* All are MMU0 defaultly. Only specialize mmu1 here. */
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#define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid))
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/* mt8167 */
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#define MT8167_SMI_LARB_MMU_EN 0xfc0
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/* SMI LARB */
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/* mt2701 */
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/* Below are about mmu enable registers, they are different in SoCs */
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/* gen1: mt2701 */
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#define REG_SMI_SECUR_CON_BASE 0x5c0
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/* every register control 8 port, register offset 0x4 */
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@ -41,20 +44,21 @@
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/* mt2701 domain should be set to 3 */
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#define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1))
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/* mt2712 */
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#define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
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#define F_MMU_EN BIT(0)
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#define BANK_SEL(id) ({ \
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/* gen2: */
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/* mt8167 */
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#define MT8167_SMI_LARB_MMU_EN 0xfc0
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/* mt8173 */
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#define MT8173_SMI_LARB_MMU_EN 0xf00
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/* general */
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#define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
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#define F_MMU_EN BIT(0)
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#define BANK_SEL(id) ({ \
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u32 _id = (id) & 0x3; \
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(_id << 8 | _id << 10 | _id << 12 | _id << 14); \
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})
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/* SMI COMMON */
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#define SMI_BUS_SEL 0x220
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#define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1)
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/* All are MMU0 defaultly. Only specialize mmu1 here. */
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#define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid))
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enum mtk_smi_type {
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MTK_SMI_GEN1,
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MTK_SMI_GEN2
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@ -140,36 +144,16 @@ mtk_smi_larb_bind(struct device *dev, struct device *master, void *data)
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return -ENODEV;
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}
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static void mtk_smi_larb_config_port_gen2_general(struct device *dev)
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static void
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mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data)
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{
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struct mtk_smi_larb *larb = dev_get_drvdata(dev);
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u32 reg;
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int i;
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if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask)
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return;
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for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
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reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
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reg |= F_MMU_EN;
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reg |= BANK_SEL(larb->bank[i]);
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writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
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}
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/* Do nothing as the iommu is always enabled. */
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}
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static void mtk_smi_larb_config_port_mt8173(struct device *dev)
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{
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struct mtk_smi_larb *larb = dev_get_drvdata(dev);
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writel(*larb->mmu, larb->base + SMI_LARB_MMU_EN);
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}
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static void mtk_smi_larb_config_port_mt8167(struct device *dev)
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{
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struct mtk_smi_larb *larb = dev_get_drvdata(dev);
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writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN);
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}
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static const struct component_ops mtk_smi_larb_component_ops = {
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.bind = mtk_smi_larb_bind,
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.unbind = mtk_smi_larb_unbind,
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};
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static void mtk_smi_larb_config_port_gen1(struct device *dev)
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{
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@ -202,26 +186,36 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev)
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}
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}
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static void
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mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data)
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static void mtk_smi_larb_config_port_mt8167(struct device *dev)
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{
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/* Do nothing as the iommu is always enabled. */
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struct mtk_smi_larb *larb = dev_get_drvdata(dev);
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writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN);
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}
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static const struct component_ops mtk_smi_larb_component_ops = {
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.bind = mtk_smi_larb_bind,
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.unbind = mtk_smi_larb_unbind,
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};
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static void mtk_smi_larb_config_port_mt8173(struct device *dev)
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{
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struct mtk_smi_larb *larb = dev_get_drvdata(dev);
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static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = {
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/* mt8173 do not need the port in larb */
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.config_port = mtk_smi_larb_config_port_mt8173,
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};
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writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN);
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}
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static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = {
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/* mt8167 do not need the port in larb */
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.config_port = mtk_smi_larb_config_port_mt8167,
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};
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static void mtk_smi_larb_config_port_gen2_general(struct device *dev)
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{
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struct mtk_smi_larb *larb = dev_get_drvdata(dev);
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u32 reg;
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int i;
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if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask)
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return;
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for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
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reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
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reg |= F_MMU_EN;
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reg |= BANK_SEL(larb->bank[i]);
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writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
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}
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}
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static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
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.port_in_larb = {
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@ -243,6 +237,16 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = {
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/* DUMMY | IPU0 | IPU1 | CCU | MDLA */
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};
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static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = {
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/* mt8167 do not need the port in larb */
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.config_port = mtk_smi_larb_config_port_mt8167,
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};
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static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = {
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/* mt8173 do not need the port in larb */
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.config_port = mtk_smi_larb_config_port_mt8173,
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};
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static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
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.config_port = mtk_smi_larb_config_port_gen2_general,
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.larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7),
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@ -254,34 +258,13 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = {
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};
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static const struct of_device_id mtk_smi_larb_of_ids[] = {
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{
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.compatible = "mediatek,mt8167-smi-larb",
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.data = &mtk_smi_larb_mt8167
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},
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{
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.compatible = "mediatek,mt8173-smi-larb",
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.data = &mtk_smi_larb_mt8173
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},
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{
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.compatible = "mediatek,mt2701-smi-larb",
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.data = &mtk_smi_larb_mt2701
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},
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{
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.compatible = "mediatek,mt2712-smi-larb",
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.data = &mtk_smi_larb_mt2712
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},
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{
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.compatible = "mediatek,mt6779-smi-larb",
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.data = &mtk_smi_larb_mt6779
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},
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{
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.compatible = "mediatek,mt8183-smi-larb",
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.data = &mtk_smi_larb_mt8183
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},
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{
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.compatible = "mediatek,mt8192-smi-larb",
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.data = &mtk_smi_larb_mt8192
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},
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{.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701},
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{.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712},
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{.compatible = "mediatek,mt6779-smi-larb", .data = &mtk_smi_larb_mt6779},
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{.compatible = "mediatek,mt8167-smi-larb", .data = &mtk_smi_larb_mt8167},
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{.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173},
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{.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183},
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{.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192},
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{}
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};
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@ -438,34 +421,13 @@ static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = {
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};
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static const struct of_device_id mtk_smi_common_of_ids[] = {
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{
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.compatible = "mediatek,mt8173-smi-common",
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.data = &mtk_smi_common_gen2,
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},
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{
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.compatible = "mediatek,mt8167-smi-common",
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.data = &mtk_smi_common_gen2,
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},
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{
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.compatible = "mediatek,mt2701-smi-common",
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.data = &mtk_smi_common_gen1,
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},
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{
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.compatible = "mediatek,mt2712-smi-common",
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.data = &mtk_smi_common_gen2,
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},
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{
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.compatible = "mediatek,mt6779-smi-common",
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.data = &mtk_smi_common_mt6779,
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},
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{
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.compatible = "mediatek,mt8183-smi-common",
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.data = &mtk_smi_common_mt8183,
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},
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{
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.compatible = "mediatek,mt8192-smi-common",
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.data = &mtk_smi_common_mt8192,
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},
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{.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1},
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{.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2},
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{.compatible = "mediatek,mt6779-smi-common", .data = &mtk_smi_common_mt6779},
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{.compatible = "mediatek,mt8167-smi-common", .data = &mtk_smi_common_gen2},
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{.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2},
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{.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183},
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{.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192},
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{}
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};
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