MIPS: ralink: add mt7628an support
Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8031/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
John Crispin
Ralf Baechle
parent
1dc5c2cfc1
commit
53263a1c68
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@ -13,6 +13,13 @@
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#ifndef _MT7620_REGS_H_
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#define _MT7620_REGS_H_
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enum mt762x_soc_type {
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MT762X_SOC_UNKNOWN = 0,
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MT762X_SOC_MT7620A,
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MT762X_SOC_MT7620N,
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MT762X_SOC_MT7628AN,
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};
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#define MT7620_SYSC_BASE 0x10000000
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#define SYSC_REG_CHIP_NAME0 0x00
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@ -27,6 +34,7 @@
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#define MT7620_CHIP_NAME0 0x3637544d
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#define MT7620_CHIP_NAME1 0x20203032
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#define MT7628_CHIP_NAME1 0x20203832
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#define SYSCFG0_XTAL_FREQ_SEL BIT(6)
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@ -71,6 +79,9 @@
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#define SYSCFG0_DRAM_TYPE_DDR1 1
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#define SYSCFG0_DRAM_TYPE_DDR2 2
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#define SYSCFG0_DRAM_TYPE_DDR2_MT7628 0
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#define SYSCFG0_DRAM_TYPE_DDR1_MT7628 1
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#define MT7620_DRAM_BASE 0x0
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#define MT7620_SDRAM_SIZE_MIN 2
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#define MT7620_SDRAM_SIZE_MAX 64
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@ -26,7 +26,7 @@ choice
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select HW_HAS_PCI
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config SOC_MT7620
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bool "MT7620"
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bool "MT7620/8"
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endchoice
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@ -37,6 +37,9 @@
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#define PMU1_CFG 0x8C
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#define DIG_SW_SEL BIT(25)
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/* is this a MT7620 or a MT7628 */
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enum mt762x_soc_type mt762x_soc;
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/* does the board have sdram or ddram */
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static int dram_type;
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@ -94,6 +97,136 @@ static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
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{ 0 }
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};
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static struct rt2880_pmx_func pwm1_grp_mt7628[] = {
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FUNC("sdcx", 3, 19, 1),
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FUNC("utif", 2, 19, 1),
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FUNC("gpio", 1, 19, 1),
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FUNC("pwm", 0, 19, 1),
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};
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static struct rt2880_pmx_func pwm0_grp_mt7628[] = {
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FUNC("sdcx", 3, 18, 1),
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FUNC("utif", 2, 18, 1),
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FUNC("gpio", 1, 18, 1),
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FUNC("pwm", 0, 18, 1),
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};
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static struct rt2880_pmx_func uart2_grp_mt7628[] = {
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FUNC("sdcx", 3, 20, 2),
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FUNC("pwm", 2, 20, 2),
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FUNC("gpio", 1, 20, 2),
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FUNC("uart", 0, 20, 2),
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};
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static struct rt2880_pmx_func uart1_grp_mt7628[] = {
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FUNC("sdcx", 3, 45, 2),
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FUNC("pwm", 2, 45, 2),
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FUNC("gpio", 1, 45, 2),
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FUNC("uart", 0, 45, 2),
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};
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static struct rt2880_pmx_func i2c_grp_mt7628[] = {
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FUNC("-", 3, 4, 2),
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FUNC("debug", 2, 4, 2),
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FUNC("gpio", 1, 4, 2),
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FUNC("i2c", 0, 4, 2),
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};
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static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("reclk", 0, 36, 1) };
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static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 37, 1) };
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static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 15, 38) };
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static struct rt2880_pmx_func spi_grp_mt7628[] = { FUNC("spi", 0, 7, 4) };
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static struct rt2880_pmx_func sd_mode_grp_mt7628[] = {
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FUNC("jtag", 3, 22, 8),
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FUNC("utif", 2, 22, 8),
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FUNC("gpio", 1, 22, 8),
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FUNC("sdcx", 0, 22, 8),
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};
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static struct rt2880_pmx_func uart0_grp_mt7628[] = {
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FUNC("-", 3, 12, 2),
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FUNC("-", 2, 12, 2),
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FUNC("gpio", 1, 12, 2),
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FUNC("uart", 0, 12, 2),
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};
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static struct rt2880_pmx_func i2s_grp_mt7628[] = {
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FUNC("antenna", 3, 0, 4),
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FUNC("pcm", 2, 0, 4),
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FUNC("gpio", 1, 0, 4),
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FUNC("i2s", 0, 0, 4),
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};
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static struct rt2880_pmx_func spi_cs1_grp_mt7628[] = {
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FUNC("-", 3, 6, 1),
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FUNC("refclk", 2, 6, 1),
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FUNC("gpio", 1, 6, 1),
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FUNC("spi", 0, 6, 1),
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};
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static struct rt2880_pmx_func spis_grp_mt7628[] = {
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FUNC("pwm", 3, 14, 4),
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FUNC("util", 2, 14, 4),
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FUNC("gpio", 1, 14, 4),
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FUNC("spis", 0, 14, 4),
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};
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static struct rt2880_pmx_func gpio_grp_mt7628[] = {
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FUNC("pcie", 3, 11, 1),
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FUNC("refclk", 2, 11, 1),
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FUNC("gpio", 1, 11, 1),
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FUNC("gpio", 0, 11, 1),
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};
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#define MT7628_GPIO_MODE_MASK 0x3
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#define MT7628_GPIO_MODE_PWM1 30
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#define MT7628_GPIO_MODE_PWM0 28
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#define MT7628_GPIO_MODE_UART2 26
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#define MT7628_GPIO_MODE_UART1 24
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#define MT7628_GPIO_MODE_I2C 20
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#define MT7628_GPIO_MODE_REFCLK 18
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#define MT7628_GPIO_MODE_PERST 16
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#define MT7628_GPIO_MODE_WDT 14
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#define MT7628_GPIO_MODE_SPI 12
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#define MT7628_GPIO_MODE_SDMODE 10
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#define MT7628_GPIO_MODE_UART0 8
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#define MT7628_GPIO_MODE_I2S 6
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#define MT7628_GPIO_MODE_CS1 4
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#define MT7628_GPIO_MODE_SPIS 2
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#define MT7628_GPIO_MODE_GPIO 0
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static struct rt2880_pmx_group mt7628an_pinmux_data[] = {
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GRP_G("pmw1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK,
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1, MT7628_GPIO_MODE_PWM1),
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GRP_G("pmw1", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK,
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1, MT7628_GPIO_MODE_PWM0),
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GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK,
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1, MT7628_GPIO_MODE_UART2),
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GRP_G("uart1", uart1_grp_mt7628, MT7628_GPIO_MODE_MASK,
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1, MT7628_GPIO_MODE_UART1),
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GRP_G("i2c", i2c_grp_mt7628, MT7628_GPIO_MODE_MASK,
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1, MT7628_GPIO_MODE_I2C),
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GRP("refclk", refclk_grp_mt7628, 1, MT7628_GPIO_MODE_REFCLK),
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GRP("perst", perst_grp_mt7628, 1, MT7628_GPIO_MODE_PERST),
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GRP("wdt", wdt_grp_mt7628, 1, MT7628_GPIO_MODE_WDT),
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GRP("spi", spi_grp_mt7628, 1, MT7628_GPIO_MODE_SPI),
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GRP_G("sdmode", sd_mode_grp_mt7628, MT7628_GPIO_MODE_MASK,
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1, MT7628_GPIO_MODE_SDMODE),
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GRP_G("uart0", uart0_grp_mt7628, MT7628_GPIO_MODE_MASK,
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1, MT7628_GPIO_MODE_UART0),
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GRP_G("i2s", i2s_grp_mt7628, MT7628_GPIO_MODE_MASK,
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1, MT7628_GPIO_MODE_I2S),
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GRP_G("spi cs1", spi_cs1_grp_mt7628, MT7628_GPIO_MODE_MASK,
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1, MT7628_GPIO_MODE_CS1),
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GRP_G("spis", spis_grp_mt7628, MT7628_GPIO_MODE_MASK,
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1, MT7628_GPIO_MODE_SPIS),
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GRP_G("gpio", gpio_grp_mt7628, MT7628_GPIO_MODE_MASK,
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1, MT7628_GPIO_MODE_GPIO),
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{ 0 }
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};
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static __init u32
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mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
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{
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@ -244,29 +377,42 @@ void __init ralink_clk_init(void)
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xtal_rate = mt7620_get_xtal_rate();
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cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
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pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
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cpu_rate = mt7620_get_cpu_rate(pll_rate);
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dram_rate = mt7620_get_dram_rate(pll_rate);
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sys_rate = mt7620_get_sys_rate(cpu_rate);
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periph_rate = mt7620_get_periph_rate(xtal_rate);
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#define RFMT(label) label ":%lu.%03luMHz "
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#define RINT(x) ((x) / 1000000)
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#define RFRAC(x) (((x) / 1000) % 1000)
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pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
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RINT(xtal_rate), RFRAC(xtal_rate),
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RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
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RINT(pll_rate), RFRAC(pll_rate));
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if (mt762x_soc == MT762X_SOC_MT7628AN) {
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if (xtal_rate == MHZ(40))
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cpu_rate = MHZ(580);
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else
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cpu_rate = MHZ(575);
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dram_rate = sys_rate = cpu_rate / 3;
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periph_rate = MHZ(40);
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ralink_clk_add("10000d00.uartlite", periph_rate);
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ralink_clk_add("10000e00.uartlite", periph_rate);
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} else {
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cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
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pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
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cpu_rate = mt7620_get_cpu_rate(pll_rate);
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dram_rate = mt7620_get_dram_rate(pll_rate);
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sys_rate = mt7620_get_sys_rate(cpu_rate);
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periph_rate = mt7620_get_periph_rate(xtal_rate);
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pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
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RINT(xtal_rate), RFRAC(xtal_rate),
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RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
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RINT(pll_rate), RFRAC(pll_rate));
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ralink_clk_add("10000500.uart", periph_rate);
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}
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pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
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RINT(cpu_rate), RFRAC(cpu_rate),
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RINT(dram_rate), RFRAC(dram_rate),
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RINT(sys_rate), RFRAC(sys_rate),
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RINT(periph_rate), RFRAC(periph_rate));
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#undef RFRAC
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#undef RINT
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#undef RFMT
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@ -274,7 +420,6 @@ void __init ralink_clk_init(void)
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ralink_clk_add("cpu", cpu_rate);
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ralink_clk_add("10000100.timer", periph_rate);
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ralink_clk_add("10000120.watchdog", periph_rate);
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ralink_clk_add("10000500.uart", periph_rate);
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ralink_clk_add("10000b00.spi", sys_rate);
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ralink_clk_add("10000c00.uartlite", periph_rate);
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ralink_clk_add("10180000.wmac", xtal_rate);
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@ -289,46 +434,9 @@ void __init ralink_of_remap(void)
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panic("Failed to remap core resources");
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}
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void prom_soc_init(struct ralink_soc_info *soc_info)
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static __init void
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mt7620_dram_init(struct ralink_soc_info *soc_info)
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{
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void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
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unsigned char *name = NULL;
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u32 n0;
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u32 n1;
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u32 rev;
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u32 cfg0;
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u32 pmu0;
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u32 pmu1;
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u32 bga;
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n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
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n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
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rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
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bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
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if (n0 != MT7620_CHIP_NAME0 || n1 != MT7620_CHIP_NAME1)
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panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
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if (bga) {
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name = "MT7620A";
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soc_info->compatible = "ralink,mt7620a-soc";
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} else {
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name = "MT7620N";
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soc_info->compatible = "ralink,mt7620n-soc";
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#ifdef CONFIG_PCI
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panic("mt7620n is only supported for non pci kernels");
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#endif
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}
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snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
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"Ralink %s ver:%u eco:%u",
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name,
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(rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
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(rev & CHIP_REV_ECO_MASK));
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cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
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dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
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switch (dram_type) {
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case SYSCFG0_DRAM_TYPE_SDRAM:
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pr_info("Board has SDRAM\n");
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@ -350,7 +458,80 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
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default:
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BUG();
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}
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}
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static __init void
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mt7628_dram_init(struct ralink_soc_info *soc_info)
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{
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switch (dram_type) {
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case SYSCFG0_DRAM_TYPE_DDR1_MT7628:
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pr_info("Board has DDR1\n");
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soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
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soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
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break;
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case SYSCFG0_DRAM_TYPE_DDR2_MT7628:
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pr_info("Board has DDR2\n");
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soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
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soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
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break;
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default:
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BUG();
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}
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}
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void prom_soc_init(struct ralink_soc_info *soc_info)
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{
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void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
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unsigned char *name = NULL;
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u32 n0;
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u32 n1;
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u32 rev;
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u32 cfg0;
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u32 pmu0;
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u32 pmu1;
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u32 bga;
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n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
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n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
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rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
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bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
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if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
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if (bga) {
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mt762x_soc = MT762X_SOC_MT7620A;
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name = "MT7620A";
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soc_info->compatible = "ralink,mt7620a-soc";
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} else {
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mt762x_soc = MT762X_SOC_MT7620N;
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name = "MT7620N";
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soc_info->compatible = "ralink,mt7620n-soc";
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#ifdef CONFIG_PCI
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panic("mt7620n is only supported for non pci kernels");
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#endif
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}
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} else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
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mt762x_soc = MT762X_SOC_MT7628AN;
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name = "MT7628AN";
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soc_info->compatible = "ralink,mt7628an-soc";
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} else {
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panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
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}
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snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
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"Ralink %s ver:%u eco:%u",
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name,
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(rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
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(rev & CHIP_REV_ECO_MASK));
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cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
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dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
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soc_info->mem_base = MT7620_DRAM_BASE;
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if (mt762x_soc == MT762X_SOC_MT7628AN)
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mt7628_dram_init(soc_info);
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else
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mt7620_dram_init(soc_info);
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pmu0 = __raw_readl(sysc + PMU0_CFG);
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pmu1 = __raw_readl(sysc + PMU1_CFG);
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@ -359,4 +540,9 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
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(pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
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pr_info("Digital PMU set to %s control\n",
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(pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
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if (mt762x_soc == MT762X_SOC_MT7628AN)
|
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rt2880_pinmux_data = mt7628an_pinmux_data;
|
||||
else
|
||||
rt2880_pinmux_data = mt7620a_pinmux_data;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue