mlxsw: reg: Add Management DownStream Device Control Register
The MDDC register allows to control downstream devices and line cards. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -11635,6 +11635,42 @@ mlxsw_reg_mddq_slot_name_unpack(const char *payload, char *slot_ascii_name)
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mlxsw_reg_mddq_slot_ascii_name_memcpy_from(payload, slot_ascii_name);
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}
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/* MDDC - Management DownStream Device Control Register
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* ----------------------------------------------------
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* This register allows to control downstream devices and line cards.
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*/
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#define MLXSW_REG_MDDC_ID 0x9163
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#define MLXSW_REG_MDDC_LEN 0x30
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MLXSW_REG_DEFINE(mddc, MLXSW_REG_MDDC_ID, MLXSW_REG_MDDC_LEN);
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/* reg_mddc_slot_index
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* Slot index. 0 is reserved.
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* Access: Index
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*/
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MLXSW_ITEM32(reg, mddc, slot_index, 0x00, 0, 4);
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/* reg_mddc_rst
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* Reset request.
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* Access: OP
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*/
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MLXSW_ITEM32(reg, mddc, rst, 0x04, 29, 1);
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/* reg_mddc_device_enable
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* When set, FW is the manager and allowed to program the downstream device.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, mddc, device_enable, 0x04, 28, 1);
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static inline void mlxsw_reg_mddc_pack(char *payload, u8 slot_index, bool rst,
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bool device_enable)
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{
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MLXSW_REG_ZERO(mddc, payload);
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mlxsw_reg_mddc_slot_index_set(payload, slot_index);
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mlxsw_reg_mddc_rst_set(payload, rst);
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mlxsw_reg_mddc_device_enable_set(payload, device_enable);
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}
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/* MFDE - Monitoring FW Debug Register
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* -----------------------------------
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*/
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@ -12955,6 +12991,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
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MLXSW_REG(mfgd),
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MLXSW_REG(mgpir),
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MLXSW_REG(mddq),
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MLXSW_REG(mddc),
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MLXSW_REG(mfde),
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MLXSW_REG(tngcr),
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MLXSW_REG(tnumt),
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