Staging: comedi: mite.c: fix coding style
- drivers/mite.c: added KERN_ facility level to printk - moved EXPORT_SYMBOL macro to follow function/variable Signed-off-by: matt mooney <mfm@muteddisk.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
matt mooney
Greg Kroah-Hartman
parent
d1a044083c
commit
5256fb8818
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@ -64,6 +64,7 @@
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MODULE_LICENSE("GPL");
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struct mite_struct *mite_devices;
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EXPORT_SYMBOL(mite_devices);
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#define TOP_OF_PAGE(x) ((x)|(~(PAGE_MASK)))
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@ -80,7 +81,7 @@ void mite_init(void)
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mite = kzalloc(sizeof(*mite), GFP_KERNEL);
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if (!mite) {
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printk("mite: allocation failed\n");
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printk(KERN_ERR "mite: allocation failed\n");
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pci_dev_put(pcidev);
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return;
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}
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@ -99,14 +100,14 @@ void mite_init(void)
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static void dump_chip_signature(u32 csigr_bits)
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{
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printk
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("mite: version = %i, type = %i, mite mode = %i, interface mode = %i\n",
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mite_csigr_version(csigr_bits), mite_csigr_type(csigr_bits),
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mite_csigr_mmode(csigr_bits), mite_csigr_imode(csigr_bits));
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printk
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("mite: num channels = %i, write post fifo depth = %i, wins = %i, iowins = %i\n",
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mite_csigr_dmac(csigr_bits), mite_csigr_wpdep(csigr_bits),
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mite_csigr_wins(csigr_bits), mite_csigr_iowins(csigr_bits));
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printk(KERN_INFO "mite: version = %i, type = %i, mite mode = %i,"
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"interface mode = %i\n",
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mite_csigr_version(csigr_bits), mite_csigr_type(csigr_bits),
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mite_csigr_mmode(csigr_bits), mite_csigr_imode(csigr_bits));
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printk(KERN_INFO "mite: num channels = %i, write post fifo depth = %i,"
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"wins = %i, iowins = %i\n",
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mite_csigr_dmac(csigr_bits), mite_csigr_wpdep(csigr_bits),
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mite_csigr_wins(csigr_bits), mite_csigr_iowins(csigr_bits));
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}
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unsigned mite_fifo_size(struct mite_struct *mite, unsigned channel)
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@ -126,7 +127,7 @@ int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
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unsigned unknown_dma_burst_bits;
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if (comedi_pci_enable(mite->pcidev, "mite")) {
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printk("error enabling mite and requesting io regions\n");
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printk(KERN_ERR "error enabling mite and requesting io regions\n");
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return -EIO;
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}
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pci_set_master(mite->pcidev);
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@ -135,27 +136,30 @@ int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
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mite->mite_phys_addr = addr;
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mite->mite_io_addr = ioremap(addr, PCI_MITE_SIZE);
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if (!mite->mite_io_addr) {
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printk("failed to remap mite io memory address\n");
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printk(KERN_ERR "Failed to remap mite io memory address\n");
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return -ENOMEM;
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}
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printk("MITE:0x%08llx mapped to %p ",
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printk(KERN_INFO "MITE:0x%08llx mapped to %p ",
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(unsigned long long)mite->mite_phys_addr, mite->mite_io_addr);
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addr = pci_resource_start(mite->pcidev, 1);
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mite->daq_phys_addr = addr;
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length = pci_resource_len(mite->pcidev, 1);
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/* In case of a 660x board, DAQ size is 8k instead of 4k (see as shown by lspci output) */
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/*
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* In case of a 660x board, DAQ size is 8k instead of 4k
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* (see as shown by lspci output)
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*/
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mite->daq_io_addr = ioremap(mite->daq_phys_addr, length);
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if (!mite->daq_io_addr) {
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printk("failed to remap daq io memory address\n");
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printk(KERN_ERR "Failed to remap daq io memory address\n");
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return -ENOMEM;
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}
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printk("DAQ:0x%08llx mapped to %p\n",
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printk(KERN_INFO "DAQ:0x%08llx mapped to %p\n",
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(unsigned long long)mite->daq_phys_addr, mite->daq_io_addr);
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if (use_iodwbsr_1) {
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writel(0, mite->mite_io_addr + MITE_IODWBSR);
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printk("mite: using I/O Window Base Size register 1\n");
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printk(KERN_INFO "mite: using I/O Window Base Size register 1\n");
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writel(mite->daq_phys_addr | WENAB |
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MITE_IODWBSR_1_WSIZE_bits(length),
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mite->mite_io_addr + MITE_IODWBSR_1);
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@ -164,11 +168,12 @@ int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
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writel(mite->daq_phys_addr | WENAB,
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mite->mite_io_addr + MITE_IODWBSR);
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}
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/* make sure dma bursts work. I got this from running a bus analyzer
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on a pxi-6281 and a pxi-6713. 6713 powered up with register value
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of 0x61f and bursts worked. 6281 powered up with register value of
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0x1f and bursts didn't work. The NI windows driver reads the register,
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then does a bitwise-or of 0x600 with it and writes it back.
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/*
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* make sure dma bursts work. I got this from running a bus analyzer
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* on a pxi-6281 and a pxi-6713. 6713 powered up with register value
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* of 0x61f and bursts worked. 6281 powered up with register value of
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* 0x1f and bursts didn't work. The NI windows driver reads the
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* register, then does a bitwise-or of 0x600 with it and writes it back.
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*/
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unknown_dma_burst_bits =
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readl(mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
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@ -179,9 +184,9 @@ int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
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csigr_bits = readl(mite->mite_io_addr + MITE_CSIGR);
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mite->num_channels = mite_csigr_dmac(csigr_bits);
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if (mite->num_channels > MAX_MITE_DMA_CHANNELS) {
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printk
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("mite: bug? chip claims to have %i dma channels. Setting to %i.\n",
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mite->num_channels, MAX_MITE_DMA_CHANNELS);
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printk(KERN_WARNING "mite: bug? chip claims to have %i dma "
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"channels. Setting to %i.\n",
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mite->num_channels, MAX_MITE_DMA_CHANNELS);
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mite->num_channels = MAX_MITE_DMA_CHANNELS;
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}
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dump_chip_signature(csigr_bits);
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@ -194,16 +199,18 @@ int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
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mite->mite_io_addr + MITE_CHCR(i));
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}
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mite->fifo_size = mite_fifo_size(mite, 0);
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printk("mite: fifo size is %i.\n", mite->fifo_size);
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printk(KERN_INFO "mite: fifo size is %i.\n", mite->fifo_size);
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mite->used = 1;
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return 0;
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}
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EXPORT_SYMBOL(mite_setup2);
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int mite_setup(struct mite_struct *mite)
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{
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return mite_setup2(mite, 0);
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}
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EXPORT_SYMBOL(mite_setup);
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void mite_cleanup(void)
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{
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@ -238,22 +245,23 @@ void mite_unsetup(struct mite_struct *mite)
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mite->used = 0;
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}
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EXPORT_SYMBOL(mite_unsetup);
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void mite_list_devices(void)
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{
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struct mite_struct *mite, *next;
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printk("Available NI device IDs:");
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printk(KERN_INFO "Available NI device IDs:");
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if (mite_devices)
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for (mite = mite_devices; mite; mite = next) {
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next = mite->next;
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printk(" 0x%04x", mite_device_id(mite));
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printk(KERN_INFO " 0x%04x", mite_device_id(mite));
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if (mite->used)
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printk("(used)");
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printk(KERN_INFO "(used)");
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}
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printk("\n");
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printk(KERN_INFO "\n");
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}
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EXPORT_SYMBOL(mite_list_devices);
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struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
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struct
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@ -265,7 +273,9 @@ struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
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unsigned long flags;
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struct mite_channel *channel = NULL;
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/* spin lock so mite_release_channel can be called safely from interrupts */
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/* spin lock so mite_release_channel can be called safely
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* from interrupts
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*/
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spin_lock_irqsave(&mite->lock, flags);
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for (i = min_channel; i <= max_channel; ++i) {
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if (mite->channel_allocated[i] == 0) {
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@ -278,6 +288,7 @@ struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
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spin_unlock_irqrestore(&mite->lock, flags);
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return channel;
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}
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EXPORT_SYMBOL(mite_request_channel_in_range);
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void mite_release_channel(struct mite_channel *mite_chan)
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{
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@ -289,8 +300,10 @@ void mite_release_channel(struct mite_channel *mite_chan)
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if (mite->channel_allocated[mite_chan->channel]) {
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mite_dma_disarm(mite_chan);
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mite_dma_reset(mite_chan);
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/* disable all channel's interrupts (do it after disarm/reset so
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MITE_CHCR reg isn't changed while dma is still active!) */
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/*
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* disable all channel's interrupts (do it after disarm/reset so
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* MITE_CHCR reg isn't changed while dma is still active!)
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*/
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writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE |
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CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE |
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CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
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@ -302,6 +315,7 @@ MITE_CHCR reg isn't changed while dma is still active!) */
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}
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spin_unlock_irqrestore(&mite->lock, flags);
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}
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EXPORT_SYMBOL(mite_release_channel);
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void mite_dma_arm(struct mite_channel *mite_chan)
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{
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@ -310,8 +324,10 @@ void mite_dma_arm(struct mite_channel *mite_chan)
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unsigned long flags;
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MDPRINTK("mite_dma_arm ch%i\n", channel);
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/* memory barrier is intended to insure any twiddling with the buffer
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is done before writing to the mite to arm dma transfer */
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/*
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* memory barrier is intended to insure any twiddling with the buffer
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* is done before writing to the mite to arm dma transfer
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*/
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smp_mb();
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/* arm */
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chor = CHOR_START;
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@ -322,6 +338,7 @@ void mite_dma_arm(struct mite_channel *mite_chan)
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spin_unlock_irqrestore(&mite->lock, flags);
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/* mite_dma_tcr(mite, channel); */
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}
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EXPORT_SYMBOL(mite_dma_arm);
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/**************************************/
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@ -354,7 +371,7 @@ int mite_buf_change(struct mite_dma_descriptor_ring *ring,
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n_links * sizeof(struct mite_dma_descriptor),
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&ring->descriptors_dma_addr, GFP_KERNEL);
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if (!ring->descriptors) {
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printk("mite: ring buffer allocation failed\n");
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printk(KERN_ERR "mite: ring buffer allocation failed\n");
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return -ENOMEM;
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}
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ring->n_links = n_links;
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@ -370,11 +387,14 @@ int mite_buf_change(struct mite_dma_descriptor_ring *ring,
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}
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ring->descriptors[n_links - 1].next =
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cpu_to_le32(ring->descriptors_dma_addr);
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/* barrier is meant to insure that all the writes to the dma descriptors
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have completed before the dma controller is commanded to read them */
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/*
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* barrier is meant to insure that all the writes to the dma descriptors
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* have completed before the dma controller is commanded to read them
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*/
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smp_wmb();
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return 0;
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}
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EXPORT_SYMBOL(mite_buf_change);
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void mite_prep_dma(struct mite_channel *mite_chan,
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unsigned int num_device_bits, unsigned int num_memory_bits)
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@ -395,16 +415,19 @@ void mite_prep_dma(struct mite_channel *mite_chan,
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* Link Complete Interrupt: interrupt every time a link
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* in MITE_RING is completed. This can generate a lot of
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* extra interrupts, but right now we update the values
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* of buf_int_ptr and buf_int_count at each interrupt. A
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* of buf_int_ptr and buf_int_count at each interrupt. A
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* better method is to poll the MITE before each user
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* "read()" to calculate the number of bytes available.
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*/
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chcr |= CHCR_SET_LC_IE;
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if (num_memory_bits == 32 && num_device_bits == 16) {
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/* Doing a combined 32 and 16 bit byteswap gets the 16 bit samples into the fifo in the right order.
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Tested doing 32 bit memory to 16 bit device transfers to the analog out of a pxi-6281,
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which has mite version = 1, type = 4. This also works for dma reads from the counters
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on e-series boards. */
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/*
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* Doing a combined 32 and 16 bit byteswap gets the 16 bit
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* samples into the fifo in the right order. Tested doing 32 bit
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* memory to 16 bit device transfers to the analog out of a
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* pxi-6281, which has mite version = 1, type = 4. This also
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* works for dma reads from the counters on e-series boards.
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*/
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chcr |= CHCR_BYTE_SWAP_DEVICE | CHCR_BYTE_SWAP_MEMORY;
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}
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if (mite_chan->dir == COMEDI_INPUT)
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@ -425,7 +448,8 @@ void mite_prep_dma(struct mite_channel *mite_chan,
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mcr |= CR_PSIZE32;
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break;
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default:
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printk("mite: bug! invalid mem bit width for dma transfer\n");
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printk(KERN_WARNING "mite: bug! invalid mem bit width for dma "
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"transfer\n");
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break;
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}
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writel(mcr, mite->mite_io_addr + MITE_MCR(mite_chan->channel));
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@ -444,7 +468,8 @@ void mite_prep_dma(struct mite_channel *mite_chan,
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dcr |= CR_PSIZE32;
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break;
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default:
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printk("mite: bug! invalid dev bit width for dma transfer\n");
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printk(KERN_WARNING "mite: bug! invalid dev bit width for dma "
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"transfer\n");
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break;
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}
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writel(dcr, mite->mite_io_addr + MITE_DCR(mite_chan->channel));
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@ -462,6 +487,7 @@ void mite_prep_dma(struct mite_channel *mite_chan,
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MDPRINTK("exit mite_prep_dma\n");
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}
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EXPORT_SYMBOL(mite_prep_dma);
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u32 mite_device_bytes_transferred(struct mite_channel *mite_chan)
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{
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@ -469,48 +495,53 @@ u32 mite_device_bytes_transferred(struct mite_channel *mite_chan)
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return readl(mite->mite_io_addr + MITE_DAR(mite_chan->channel));
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}
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u32 mite_bytes_in_transit(struct mite_channel * mite_chan)
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u32 mite_bytes_in_transit(struct mite_channel *mite_chan)
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{
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struct mite_struct *mite = mite_chan->mite;
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return readl(mite->mite_io_addr +
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MITE_FCR(mite_chan->channel)) & 0x000000FF;
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}
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EXPORT_SYMBOL(mite_bytes_in_transit);
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/* returns lower bound for number of bytes transferred from device to memory */
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u32 mite_bytes_written_to_memory_lb(struct mite_channel * mite_chan)
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/* returns lower bound for number of bytes transferred from device to memory */
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u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan)
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{
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u32 device_byte_count;
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device_byte_count = mite_device_bytes_transferred(mite_chan);
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return device_byte_count - mite_bytes_in_transit(mite_chan);
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}
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EXPORT_SYMBOL(mite_bytes_written_to_memory_lb);
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/* returns upper bound for number of bytes transferred from device to memory */
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u32 mite_bytes_written_to_memory_ub(struct mite_channel * mite_chan)
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/* returns upper bound for number of bytes transferred from device to memory */
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u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan)
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{
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u32 in_transit_count;
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in_transit_count = mite_bytes_in_transit(mite_chan);
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return mite_device_bytes_transferred(mite_chan) - in_transit_count;
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}
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EXPORT_SYMBOL(mite_bytes_written_to_memory_ub);
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/* returns lower bound for number of bytes read from memory for transfer to device */
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u32 mite_bytes_read_from_memory_lb(struct mite_channel * mite_chan)
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/* returns lower bound for number of bytes read from memory to device */
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u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan)
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{
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u32 device_byte_count;
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device_byte_count = mite_device_bytes_transferred(mite_chan);
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return device_byte_count + mite_bytes_in_transit(mite_chan);
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}
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EXPORT_SYMBOL(mite_bytes_read_from_memory_lb);
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/* returns upper bound for number of bytes read from memory for transfer to device */
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u32 mite_bytes_read_from_memory_ub(struct mite_channel * mite_chan)
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/* returns upper bound for number of bytes read from memory to device */
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u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan)
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{
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u32 in_transit_count;
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in_transit_count = mite_bytes_in_transit(mite_chan);
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return mite_device_bytes_transferred(mite_chan) + in_transit_count;
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}
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EXPORT_SYMBOL(mite_bytes_read_from_memory_ub);
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unsigned mite_dma_tcr(struct mite_channel *mite_chan)
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{
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@ -525,6 +556,7 @@ unsigned mite_dma_tcr(struct mite_channel *mite_chan)
|
|||
|
||||
return tcr;
|
||||
}
|
||||
EXPORT_SYMBOL(mite_dma_tcr);
|
||||
|
||||
void mite_dma_disarm(struct mite_channel *mite_chan)
|
||||
{
|
||||
|
|
@ -535,6 +567,7 @@ void mite_dma_disarm(struct mite_channel *mite_chan)
|
|||
chor = CHOR_ABORT;
|
||||
writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
|
||||
}
|
||||
EXPORT_SYMBOL(mite_dma_disarm);
|
||||
|
||||
int mite_sync_input_dma(struct mite_channel *mite_chan,
|
||||
struct comedi_async *async)
|
||||
|
|
@ -544,7 +577,7 @@ int mite_sync_input_dma(struct mite_channel *mite_chan,
|
|||
const unsigned bytes_per_scan = cfc_bytes_per_scan(async->subdevice);
|
||||
|
||||
old_alloc_count = async->buf_write_alloc_count;
|
||||
/* write alloc as much as we can */
|
||||
/* write alloc as much as we can */
|
||||
comedi_buf_write_alloc(async, async->prealloc_bufsz);
|
||||
|
||||
nbytes = mite_bytes_written_to_memory_lb(mite_chan);
|
||||
|
|
@ -571,6 +604,7 @@ int mite_sync_input_dma(struct mite_channel *mite_chan,
|
|||
async->events |= COMEDI_CB_BLOCK;
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(mite_sync_input_dma);
|
||||
|
||||
int mite_sync_output_dma(struct mite_channel *mite_chan,
|
||||
struct comedi_async *async)
|
||||
|
|
@ -593,7 +627,7 @@ int mite_sync_output_dma(struct mite_channel *mite_chan,
|
|||
(int)(nbytes_ub - stop_count) > 0)
|
||||
nbytes_ub = stop_count;
|
||||
if ((int)(nbytes_ub - old_alloc_count) > 0) {
|
||||
printk("mite: DMA underrun\n");
|
||||
printk(KERN_ERR "mite: DMA underrun\n");
|
||||
async->events |= COMEDI_CB_OVERFLOW;
|
||||
return -1;
|
||||
}
|
||||
|
|
@ -607,6 +641,7 @@ int mite_sync_output_dma(struct mite_channel *mite_chan,
|
|||
}
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(mite_sync_output_dma);
|
||||
|
||||
unsigned mite_get_status(struct mite_channel *mite_chan)
|
||||
{
|
||||
|
|
@ -625,6 +660,7 @@ unsigned mite_get_status(struct mite_channel *mite_chan)
|
|||
spin_unlock_irqrestore(&mite->lock, flags);
|
||||
return status;
|
||||
}
|
||||
EXPORT_SYMBOL(mite_get_status);
|
||||
|
||||
int mite_done(struct mite_channel *mite_chan)
|
||||
{
|
||||
|
|
@ -638,6 +674,7 @@ int mite_done(struct mite_channel *mite_chan)
|
|||
spin_unlock_irqrestore(&mite->lock, flags);
|
||||
return done;
|
||||
}
|
||||
EXPORT_SYMBOL(mite_done);
|
||||
|
||||
#ifdef DEBUG_MITE
|
||||
|
||||
|
|
@ -719,46 +756,51 @@ void mite_dump_regs(struct mite_channel *mite_chan)
|
|||
unsigned long addr = 0;
|
||||
unsigned long temp = 0;
|
||||
|
||||
printk("mite_dump_regs ch%i\n", mite_chan->channel);
|
||||
printk("mite address is =0x%08lx\n", mite_io_addr);
|
||||
printk(KERN_DEBUG "mite_dump_regs ch%i\n", mite_chan->channel);
|
||||
printk(KERN_DEBUG "mite address is =0x%08lx\n", mite_io_addr);
|
||||
|
||||
addr = mite_io_addr + MITE_CHOR(channel);
|
||||
printk("mite status[CHOR]at 0x%08lx =0x%08lx\n", addr, temp =
|
||||
readl(addr));
|
||||
printk(KERN_DEBUG "mite status[CHOR]at 0x%08lx =0x%08lx\n", addr,
|
||||
temp = readl(addr));
|
||||
mite_decode(mite_CHOR_strings, temp);
|
||||
addr = mite_io_addr + MITE_CHCR(channel);
|
||||
printk("mite status[CHCR]at 0x%08lx =0x%08lx\n", addr, temp =
|
||||
readl(addr));
|
||||
printk(KERN_DEBUG "mite status[CHCR]at 0x%08lx =0x%08lx\n", addr,
|
||||
temp = readl(addr));
|
||||
mite_decode(mite_CHCR_strings, temp);
|
||||
addr = mite_io_addr + MITE_TCR(channel);
|
||||
printk("mite status[TCR] at 0x%08lx =0x%08x\n", addr, readl(addr));
|
||||
addr = mite_io_addr + MITE_MCR(channel);
|
||||
printk("mite status[MCR] at 0x%08lx =0x%08lx\n", addr, temp =
|
||||
printk(KERN_DEBUG "mite status[TCR] at 0x%08lx =0x%08x\n", addr,
|
||||
readl(addr));
|
||||
addr = mite_io_addr + MITE_MCR(channel);
|
||||
printk(KERN_DEBUG "mite status[MCR] at 0x%08lx =0x%08lx\n", addr,
|
||||
temp = readl(addr));
|
||||
mite_decode(mite_MCR_strings, temp);
|
||||
|
||||
addr = mite_io_addr + MITE_MAR(channel);
|
||||
printk("mite status[MAR] at 0x%08lx =0x%08x\n", addr, readl(addr));
|
||||
addr = mite_io_addr + MITE_DCR(channel);
|
||||
printk("mite status[DCR] at 0x%08lx =0x%08lx\n", addr, temp =
|
||||
printk(KERN_DEBUG "mite status[MAR] at 0x%08lx =0x%08x\n", addr,
|
||||
readl(addr));
|
||||
addr = mite_io_addr + MITE_DCR(channel);
|
||||
printk(KERN_DEBUG "mite status[DCR] at 0x%08lx =0x%08lx\n", addr,
|
||||
temp = readl(addr));
|
||||
mite_decode(mite_DCR_strings, temp);
|
||||
addr = mite_io_addr + MITE_DAR(channel);
|
||||
printk("mite status[DAR] at 0x%08lx =0x%08x\n", addr, readl(addr));
|
||||
addr = mite_io_addr + MITE_LKCR(channel);
|
||||
printk("mite status[LKCR]at 0x%08lx =0x%08lx\n", addr, temp =
|
||||
printk(KERN_DEBUG "mite status[DAR] at 0x%08lx =0x%08x\n", addr,
|
||||
readl(addr));
|
||||
addr = mite_io_addr + MITE_LKCR(channel);
|
||||
printk(KERN_DEBUG "mite status[LKCR]at 0x%08lx =0x%08lx\n", addr,
|
||||
temp = readl(addr));
|
||||
mite_decode(mite_LKCR_strings, temp);
|
||||
addr = mite_io_addr + MITE_LKAR(channel);
|
||||
printk("mite status[LKAR]at 0x%08lx =0x%08x\n", addr, readl(addr));
|
||||
|
||||
addr = mite_io_addr + MITE_CHSR(channel);
|
||||
printk("mite status[CHSR]at 0x%08lx =0x%08lx\n", addr, temp =
|
||||
printk(KERN_DEBUG "mite status[LKAR]at 0x%08lx =0x%08x\n", addr,
|
||||
readl(addr));
|
||||
addr = mite_io_addr + MITE_CHSR(channel);
|
||||
printk(KERN_DEBUG "mite status[CHSR]at 0x%08lx =0x%08lx\n", addr,
|
||||
temp = readl(addr));
|
||||
mite_decode(mite_CHSR_strings, temp);
|
||||
addr = mite_io_addr + MITE_FCR(channel);
|
||||
printk("mite status[FCR] at 0x%08lx =0x%08x\n\n", addr, readl(addr));
|
||||
printk(KERN_DEBUG "mite status[FCR] at 0x%08lx =0x%08x\n\n", addr,
|
||||
readl(addr));
|
||||
}
|
||||
EXPORT_SYMBOL(mite_dump_regs);
|
||||
|
||||
static void mite_decode(char **bit_str, unsigned int bits)
|
||||
{
|
||||
|
|
@ -766,10 +808,11 @@ static void mite_decode(char **bit_str, unsigned int bits)
|
|||
|
||||
for (i = 31; i >= 0; i--) {
|
||||
if (bits & (1 << i))
|
||||
printk(" %s", bit_str[i]);
|
||||
printk(KERN_DEBUG " %s", bit_str[i]);
|
||||
}
|
||||
printk("\n");
|
||||
printk(KERN_DEBUG "\n");
|
||||
}
|
||||
EXPORT_SYMBOL(mite_decode);
|
||||
#endif
|
||||
|
||||
#ifdef MODULE
|
||||
|
|
@ -785,36 +828,4 @@ void __exit cleanup_module(void)
|
|||
{
|
||||
mite_cleanup();
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(mite_dma_tcr);
|
||||
EXPORT_SYMBOL(mite_dma_arm);
|
||||
EXPORT_SYMBOL(mite_dma_disarm);
|
||||
EXPORT_SYMBOL(mite_sync_input_dma);
|
||||
EXPORT_SYMBOL(mite_sync_output_dma);
|
||||
EXPORT_SYMBOL(mite_setup);
|
||||
EXPORT_SYMBOL(mite_setup2);
|
||||
EXPORT_SYMBOL(mite_unsetup);
|
||||
#if 0
|
||||
EXPORT_SYMBOL(mite_kvmem_segment_load);
|
||||
EXPORT_SYMBOL(mite_ll_from_kvmem);
|
||||
EXPORT_SYMBOL(mite_setregs);
|
||||
#endif
|
||||
EXPORT_SYMBOL(mite_devices);
|
||||
EXPORT_SYMBOL(mite_list_devices);
|
||||
EXPORT_SYMBOL(mite_request_channel_in_range);
|
||||
EXPORT_SYMBOL(mite_release_channel);
|
||||
EXPORT_SYMBOL(mite_prep_dma);
|
||||
EXPORT_SYMBOL(mite_buf_change);
|
||||
EXPORT_SYMBOL(mite_bytes_written_to_memory_lb);
|
||||
EXPORT_SYMBOL(mite_bytes_written_to_memory_ub);
|
||||
EXPORT_SYMBOL(mite_bytes_read_from_memory_lb);
|
||||
EXPORT_SYMBOL(mite_bytes_read_from_memory_ub);
|
||||
EXPORT_SYMBOL(mite_bytes_in_transit);
|
||||
EXPORT_SYMBOL(mite_get_status);
|
||||
EXPORT_SYMBOL(mite_done);
|
||||
#ifdef DEBUG_MITE
|
||||
EXPORT_SYMBOL(mite_decode);
|
||||
EXPORT_SYMBOL(mite_dump_regs);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue