ARM: dts: meson: add the TIMER B/C/D interrupts

The timer on Meson6/Meson8/Meson8b SoCs has four internal timer events.
For each of these a separate interrupt exists.
Pass these interrupts to allow using the timers other than TIMER A.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This commit is contained in:
Martin Blumenstingl 2018-11-16 21:42:34 +01:00 committed by Kevin Hilman
parent 7e26335b1a
commit 523b8b31d3
1 changed files with 4 additions and 1 deletions

View File

@ -200,7 +200,10 @@
timer@9940 {
compatible = "amlogic,meson6-timer";
reg = <0x9940 0x18>;
interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 11 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
};
};