OMAPDSS: DSI: fix lane handling when entering ULPS
The current code always enters ULPS for 3 lanes. This is not right, as there could be only 2 lanes used, and on OMAP4 we have 5 lanes. Fix the code to put all used lanes into ULPS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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@ -3517,7 +3517,8 @@ static int dsi_enter_ulps(struct platform_device *dsidev)
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{
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struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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DECLARE_COMPLETION_ONSTACK(completion);
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int r;
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int r, i;
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unsigned mask;
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DSSDBGF();
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@ -3560,10 +3561,16 @@ static int dsi_enter_ulps(struct platform_device *dsidev)
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if (r)
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return r;
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mask = 0;
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for (i = 0; i < dsi->num_lanes_supported; ++i) {
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if (dsi->lanes[i].function == DSI_LANE_UNUSED)
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continue;
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mask |= 1 << i;
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}
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/* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
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/* LANEx_ULPS_SIG2 */
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REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, (1 << 0) | (1 << 1) | (1 << 2),
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7, 5);
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REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5);
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/* flush posted write and wait for SCP interface to finish the write */
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dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
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@ -3579,8 +3586,7 @@ static int dsi_enter_ulps(struct platform_device *dsidev)
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DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
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/* Reset LANEx_ULPS_SIG2 */
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REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, (0 << 0) | (0 << 1) | (0 << 2),
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7, 5);
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REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5);
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/* flush posted write and wait for SCP interface to finish the write */
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dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
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