dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D
CMU_G3D generates Gondul GPU and bus clocks for BLK_G3D. Add clock indices and binding documentation for CMU_G3D. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20230223042133.26551-2-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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@ -37,6 +37,7 @@ properties:
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- samsung,exynos850-cmu-cmgp
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- samsung,exynos850-cmu-core
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- samsung,exynos850-cmu-dpu
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- samsung,exynos850-cmu-g3d
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- samsung,exynos850-cmu-hsi
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- samsung,exynos850-cmu-is
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- samsung,exynos850-cmu-mfcmscl
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@ -169,6 +170,24 @@ allOf:
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- const: oscclk
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- const: dout_dpu
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos850-cmu-g3d
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: G3D clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: dout_g3d_switch
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- if:
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properties:
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compatible:
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@ -85,7 +85,10 @@
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#define CLK_DOUT_MFCMSCL_M2M 73
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#define CLK_DOUT_MFCMSCL_MCSC 74
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#define CLK_DOUT_MFCMSCL_JPEG 75
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#define TOP_NR_CLK 76
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#define CLK_MOUT_G3D_SWITCH 76
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#define CLK_GOUT_G3D_SWITCH 77
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#define CLK_DOUT_G3D_SWITCH 78
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#define TOP_NR_CLK 79
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/* CMU_APM */
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#define CLK_RCO_I3C_PMIC 1
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@ -195,6 +198,21 @@
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#define CLK_GOUT_SYSREG_CMGP_PCLK 15
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#define CMGP_NR_CLK 16
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/* CMU_G3D */
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#define CLK_FOUT_G3D_PLL 1
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#define CLK_MOUT_G3D_PLL 2
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#define CLK_MOUT_G3D_SWITCH_USER 3
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#define CLK_MOUT_G3D_BUSD 4
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#define CLK_DOUT_G3D_BUSP 5
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#define CLK_GOUT_G3D_CMU_G3D_PCLK 6
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#define CLK_GOUT_G3D_GPU_CLK 7
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#define CLK_GOUT_G3D_TZPC_PCLK 8
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#define CLK_GOUT_G3D_GRAY2BIN_CLK 9
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#define CLK_GOUT_G3D_BUSD_CLK 10
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#define CLK_GOUT_G3D_BUSP_CLK 11
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#define CLK_GOUT_G3D_SYSREG_PCLK 12
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#define G3D_NR_CLK 13
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/* CMU_HSI */
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#define CLK_MOUT_HSI_BUS_USER 1
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#define CLK_MOUT_HSI_MMC_CARD_USER 2
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