phy: qcom-qmp: add QMP V2 PCIe PHY support for ipq60xx
Based on code from downstream Codeaurora tree. The ipq60xx has one gen3 PCIe port. Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Link: https://lore.kernel.org/r/e24f2bedb8a7346018b58136bcb0a4004d8677a0.1620203062.git.baruch@tkos.co.il Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Selvam Sathappan Periakaruppan
Vinod Koul
parent
9f7368ff12
commit
520264db3b
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@ -143,6 +143,13 @@ static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_PCS_READY_STATUS] = 0x168,
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};
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static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_SW_RESET] = 0x00,
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[QPHY_START_CTRL] = 0x44,
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[QPHY_PCS_STATUS] = 0x14,
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[QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
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};
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static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_COM_SW_RESET] = 0x400,
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[QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
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@ -614,6 +621,113 @@ static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
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};
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static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
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QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
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QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
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QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
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QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
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QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
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QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
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QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
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QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
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QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
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QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
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QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
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QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
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QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
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QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
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QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
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QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
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QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
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QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
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QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
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QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
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QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
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QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
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QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
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QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
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QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
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QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
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QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
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QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
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QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
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QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
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QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
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QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
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};
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static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
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};
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static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
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QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
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QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
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QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
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QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
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QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
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QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
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};
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static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
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QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
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QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
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QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
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QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
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QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
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QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
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QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
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QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
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QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
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QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
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QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
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QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
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QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
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QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
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QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
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QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
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};
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static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
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QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
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@ -2744,6 +2858,36 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
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.pwrdn_delay_max = 1005, /* us */
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};
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static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
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.type = PHY_TYPE_PCIE,
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.nlanes = 1,
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.serdes_tbl = ipq6018_pcie_serdes_tbl,
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.serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
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.tx_tbl = ipq6018_pcie_tx_tbl,
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.tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
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.rx_tbl = ipq6018_pcie_rx_tbl,
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.rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
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.pcs_tbl = ipq6018_pcie_pcs_tbl,
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.pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
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.clk_list = ipq8074_pciephy_clk_l,
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.num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
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.reset_list = ipq8074_pciephy_reset_l,
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.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
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.vreg_list = NULL,
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.num_vregs = 0,
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.regs = ipq_pciephy_gen3_regs_layout,
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.start_ctrl = SERDES_START | PCS_START,
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.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
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.has_phy_com_ctrl = false,
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.has_lane_rst = false,
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.has_pwrdn_delay = true,
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.pwrdn_delay_min = 995, /* us */
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.pwrdn_delay_max = 1005, /* us */
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};
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static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
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.type = PHY_TYPE_PCIE,
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.nlanes = 1,
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@ -4927,6 +5071,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
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}, {
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.compatible = "qcom,ipq8074-qmp-pcie-phy",
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.data = &ipq8074_pciephy_cfg,
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}, {
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.compatible = "qcom,ipq6018-qmp-pcie-phy",
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.data = &ipq6018_pciephy_cfg,
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}, {
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.compatible = "qcom,sc7180-qmp-usb3-phy",
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.data = &sc7180_usb3phy_cfg,
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@ -6,6 +6,138 @@
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#ifndef QCOM_PHY_QMP_H_
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#define QCOM_PHY_QMP_H_
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/* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */
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#define QSERDES_PLL_BG_TIMER 0x00c
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#define QSERDES_PLL_SSC_PER1 0x01c
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#define QSERDES_PLL_SSC_PER2 0x020
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#define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
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#define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
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#define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c
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#define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030
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#define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c
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#define QSERDES_PLL_CLK_ENABLE1 0x040
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#define QSERDES_PLL_SYS_CLK_CTRL 0x044
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#define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048
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#define QSERDES_PLL_PLL_IVCO 0x050
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#define QSERDES_PLL_LOCK_CMP1_MODE0 0x054
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#define QSERDES_PLL_LOCK_CMP2_MODE0 0x058
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#define QSERDES_PLL_LOCK_CMP1_MODE1 0x060
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#define QSERDES_PLL_LOCK_CMP2_MODE1 0x064
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#define QSERDES_PLL_BG_TRIM 0x074
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#define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078
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#define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c
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#define QSERDES_PLL_CP_CTRL_MODE0 0x080
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#define QSERDES_PLL_CP_CTRL_MODE1 0x084
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#define QSERDES_PLL_PLL_RCTRL_MODE0 0x088
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#define QSERDES_PLL_PLL_RCTRL_MODE1 0x08C
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#define QSERDES_PLL_PLL_CCTRL_MODE0 0x090
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#define QSERDES_PLL_PLL_CCTRL_MODE1 0x094
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#define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a4
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#define QSERDES_PLL_SYSCLK_EN_SEL 0x0a8
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#define QSERDES_PLL_RESETSM_CNTRL 0x0b0
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#define QSERDES_PLL_LOCK_CMP_EN 0x0c4
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#define QSERDES_PLL_DEC_START_MODE0 0x0cc
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#define QSERDES_PLL_DEC_START_MODE1 0x0d0
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#define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8
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#define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc
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#define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0
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#define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4
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#define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8
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#define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0eC
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#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100
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#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104
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#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108
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#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c
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#define QSERDES_PLL_VCO_TUNE_MAP 0x120
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#define QSERDES_PLL_VCO_TUNE1_MODE0 0x124
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#define QSERDES_PLL_VCO_TUNE2_MODE0 0x128
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#define QSERDES_PLL_VCO_TUNE1_MODE1 0x12c
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#define QSERDES_PLL_VCO_TUNE2_MODE1 0x130
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#define QSERDES_PLL_VCO_TUNE_TIMER1 0x13c
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#define QSERDES_PLL_VCO_TUNE_TIMER2 0x140
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#define QSERDES_PLL_CLK_SELECT 0x16c
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#define QSERDES_PLL_HSCLK_SEL 0x170
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#define QSERDES_PLL_CORECLK_DIV 0x17c
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#define QSERDES_PLL_CORE_CLK_EN 0x184
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#define QSERDES_PLL_CMN_CONFIG 0x18c
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#define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194
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#define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4
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/* QMP V2 PHY for PCIE gen3 ports - QSERDES TX registers */
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#define QSERDES_TX0_RES_CODE_LANE_OFFSET_TX 0x03c
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#define QSERDES_TX0_HIGHZ_DRVR_EN 0x058
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#define QSERDES_TX0_LANE_MODE_1 0x084
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#define QSERDES_TX0_RCV_DETECT_LVL_2 0x09c
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/* QMP V2 PHY for PCIE gen3 ports - QSERDES RX registers */
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#define QSERDES_RX0_UCDR_FO_GAIN 0x008
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#define QSERDES_RX0_UCDR_SO_GAIN 0x014
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#define QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE 0x034
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#define QSERDES_RX0_UCDR_PI_CONTROLS 0x044
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#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2 0x0ec
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#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3 0x0f0
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#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4 0x0f4
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#define QSERDES_RX0_RX_IDAC_TSETTLE_LOW 0x0f8
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#define QSERDES_RX0_RX_IDAC_TSETTLE_HIGH 0x0fc
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#define QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
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#define QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2 0x114
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#define QSERDES_RX0_SIGDET_ENABLES 0x118
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#define QSERDES_RX0_SIGDET_CNTRL 0x11c
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#define QSERDES_RX0_SIGDET_DEGLITCH_CNTRL 0x124
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#define QSERDES_RX0_RX_MODE_00_LOW 0x170
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#define QSERDES_RX0_RX_MODE_00_HIGH 0x174
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#define QSERDES_RX0_RX_MODE_00_HIGH2 0x178
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#define QSERDES_RX0_RX_MODE_00_HIGH3 0x17c
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#define QSERDES_RX0_RX_MODE_00_HIGH4 0x180
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#define QSERDES_RX0_RX_MODE_01_LOW 0x184
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#define QSERDES_RX0_RX_MODE_01_HIGH 0x188
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#define QSERDES_RX0_RX_MODE_01_HIGH2 0x18c
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#define QSERDES_RX0_RX_MODE_01_HIGH3 0x190
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#define QSERDES_RX0_RX_MODE_01_HIGH4 0x194
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#define QSERDES_RX0_RX_MODE_10_LOW 0x198
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#define QSERDES_RX0_RX_MODE_10_HIGH 0x19c
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#define QSERDES_RX0_RX_MODE_10_HIGH2 0x1a0
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#define QSERDES_RX0_RX_MODE_10_HIGH3 0x1a4
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#define QSERDES_RX0_RX_MODE_10_HIGH4 0x1a8
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#define QSERDES_RX0_DFE_EN_TIMER 0x1b4
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|
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/* QMP V2 PHY for PCIE gen3 ports - PCS registers */
|
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|
||||
#define PCS_COM_FLL_CNTRL1 0x098
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#define PCS_COM_FLL_CNTRL2 0x09c
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#define PCS_COM_FLL_CNT_VAL_L 0x0a0
|
||||
#define PCS_COM_FLL_CNT_VAL_H_TOL 0x0a4
|
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#define PCS_COM_FLL_MAN_CODE 0x0a8
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#define PCS_COM_REFGEN_REQ_CONFIG1 0x0dc
|
||||
#define PCS_COM_G12S1_TXDEEMPH_M3P5DB 0x16c
|
||||
#define PCS_COM_RX_SIGDET_LVL 0x188
|
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#define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4
|
||||
#define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8
|
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#define PCS_COM_RX_DCC_CAL_CONFIG 0x1d8
|
||||
#define PCS_COM_EQ_CONFIG5 0x1ec
|
||||
|
||||
/* QMP V2 PHY for PCIE gen3 ports - PCS Misc registers */
|
||||
|
||||
#define PCS_PCIE_POWER_STATE_CONFIG2 0x40c
|
||||
#define PCS_PCIE_POWER_STATE_CONFIG4 0x414
|
||||
#define PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x41c
|
||||
#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x440
|
||||
#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x444
|
||||
#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x448
|
||||
#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x44c
|
||||
#define PCS_PCIE_OSC_DTCT_CONFIG2 0x45c
|
||||
#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x478
|
||||
#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x480
|
||||
#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x484
|
||||
#define PCS_PCIE_OSC_DTCT_ACTIONS 0x490
|
||||
#define PCS_PCIE_EQ_CONFIG1 0x4a0
|
||||
#define PCS_PCIE_EQ_CONFIG2 0x4a4
|
||||
#define PCS_PCIE_PRESET_P10_PRE 0x4bc
|
||||
#define PCS_PCIE_PRESET_P10_POST 0x4e0
|
||||
|
||||
/* Only for QMP V2 PHY - QSERDES COM registers */
|
||||
#define QSERDES_COM_BG_TIMER 0x00c
|
||||
#define QSERDES_COM_SSC_EN_CENTER 0x010
|
||||
|
|
|
|||
Loading…
Reference in New Issue