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Staging: rt2860: remove dead RT_BIG_ENDIAN code 

Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Bartlomiej Zolnierkiewicz 2009-04-26 16:05:39 +02:00 committed by Greg Kroah-Hartman
parent b34b33ca5d
commit 51f94a7b1f
18 changed files with 69 additions and 2081 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/staging/rt2860/2860_main_dev.c
View File

@ -1167,9 +1167,7 @@ VOID RT28xx_UpdateBeaconToAsic(
else
{
ptr = (PUCHAR)&pAd->BeaconTxWI;
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange(ptr, TYPE_TXWI);
#endif
for (i=0; i<TXWI_SIZE; i+=4) // 16-byte TXWI field
{
UINT32 longptr = *ptr + (*(ptr+1)<<8) + (*(ptr+2)<<16) + (*(ptr+3)<<24);

25
drivers/staging/rt2860/common/2860_rtmp_init.c
View File

@ -173,9 +173,6 @@ NDIS_STATUS RTMPAllocTxRxRingMemory(
pTxD->SDPtr0 = BufBasePaLow;
// advance to next ring descriptor address
pTxD->DMADONE = 1;
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#endif
RingBasePaLow += TXD_SIZE;
RingBaseVa = (PUCHAR) RingBaseVa + TXD_SIZE;
@ -236,9 +233,6 @@ NDIS_STATUS RTMPAllocTxRxRingMemory(
pTxD = (PTXD_STRUC) pAd->MgmtRing.Cell[index].AllocVa;
pTxD->DMADONE = 1;
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#endif
// no pre-allocated buffer required in MgmtRing for scatter-gather case
}
DBGPRINT(RT_DEBUG_TRACE, ("MGMT Ring: total %d entry allocated\n", index));
@ -318,10 +312,6 @@ NDIS_STATUS RTMPAllocTxRxRingMemory(
pRxD = (PRXD_STRUC) pAd->RxRing.Cell[index].AllocVa;
pRxD->SDP0 = RTMP_GetPhysicalAddressLow(pDmaBuf->AllocPa);
pRxD->DDONE = 0;
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pRxD, TYPE_RXD);
#endif
}
DBGPRINT(RT_DEBUG_TRACE, ("Rx Ring: total %d entry allocated\n", index));
@ -821,10 +811,6 @@ PNDIS_PACKET GetPacketFromRxRing(
IN OUT UINT32 *pRxPending)
{
PRXD_STRUC pRxD;
#ifdef RT_BIG_ENDIAN
PRXD_STRUC pDestRxD;
RXD_STRUC RxD;
#endif
PNDIS_PACKET pRxPacket = NULL;
PNDIS_PACKET pNewPacket;
PVOID AllocVa;
@ -853,15 +839,8 @@ PNDIS_PACKET GetPacketFromRxRing(
}
#ifdef RT_BIG_ENDIAN
pDestRxD = (PRXD_STRUC) pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].AllocVa;
RxD = *pDestRxD;
pRxD = &RxD;
RTMPDescriptorEndianChange((PUCHAR)pRxD, TYPE_RXD);
#else
// Point to Rx indexed rx ring descriptor
pRxD = (PRXD_STRUC) pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].AllocVa;
#endif
if (pRxD->DDONE == 0)
{
@ -904,10 +883,6 @@ PNDIS_PACKET GetPacketFromRxRing(
*pRxPending = *pRxPending - 1;
// update rx descriptor and kick rx
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pRxD, TYPE_RXD);
WriteBackToDescriptor((PUCHAR)pDestRxD, (PUCHAR)pRxD, FALSE, TYPE_RXD);
#endif
INC_RING_INDEX(pAd->RxRing.RxSwReadIdx, RX_RING_SIZE);
pAd->RxRing.RxCpuIdx = (pAd->RxRing.RxSwReadIdx == 0) ? (RX_RING_SIZE-1) : (pAd->RxRing.RxSwReadIdx-1);

7
drivers/staging/rt2860/common/action.h
View File

@ -41,17 +41,10 @@
typedef struct PACKED __HT_INFO_OCTET
{
#ifdef RT_BIG_ENDIAN
UCHAR Reserved:5;
UCHAR STA_Channel_Width:1;
UCHAR Forty_MHz_Intolerant:1;
UCHAR Request:1;
#else
UCHAR Request:1;
UCHAR Forty_MHz_Intolerant:1;
UCHAR STA_Channel_Width:1;
UCHAR Reserved:5;
#endif
} HT_INFORMATION_OCTET;

64
drivers/staging/rt2860/common/cmm_data.c
View File

@ -300,10 +300,6 @@ NDIS_STATUS MlmeHardTransmitTxRing(
PUCHAR pSrcBufVA;
UINT SrcBufLen;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
PHEADER_802_11 pHeader_802_11;
BOOLEAN bAckRequired, bInsertTimestamp;
ULONG SrcBufPA;
@ -335,14 +331,7 @@ NDIS_STATUS MlmeHardTransmitTxRing(
SwIdx = pAd->TxRing[QueIdx].TxCpuIdx;
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pAd->TxRing[QueIdx].Cell[SwIdx].AllocVa;
#else
pDestTxD = (PTXD_STRUC)pAd->TxRing[QueIdx].Cell[SwIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#endif
if (pAd->TxRing[QueIdx].Cell[SwIdx].pNdisPacket)
{
@ -438,9 +427,6 @@ NDIS_STATUS MlmeHardTransmitTxRing(
return (NDIS_STATUS_FAILURE);
}
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (PUCHAR)pHeader_802_11, DIR_WRITE, FALSE);
#endif
//
// fill scatter-and-gather buffer list into TXD. Internally created NDIS PACKET
// should always has only one ohysical buffer, and the whole frame size equals
@ -470,9 +456,7 @@ NDIS_STATUS MlmeHardTransmitTxRing(
pAd->TxRing[QueIdx].Cell[SwIdx].pNdisPacket = pPacket;
pAd->TxRing[QueIdx].Cell[SwIdx].pNextNdisPacket = NULL;
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange((PUCHAR)pFirstTxWI, TYPE_TXWI);
#endif
SrcBufPA = PCI_MAP_SINGLE(pAd, pSrcBufVA, SrcBufLen, 0, PCI_DMA_TODEVICE);
@ -484,11 +468,6 @@ NDIS_STATUS MlmeHardTransmitTxRing(
pTxD->SDPtr0 = SrcBufPA;
pTxD->DMADONE = 0;
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif
pAd->RalinkCounters.KickTxCount++;
pAd->RalinkCounters.OneSecTxDoneCount++;
@ -639,10 +618,6 @@ NDIS_STATUS MlmeHardTransmitMgmtRing(
return (NDIS_STATUS_FAILURE);
}
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (PUCHAR)pHeader_802_11, DIR_WRITE, FALSE);
#endif
//
// fill scatter-and-gather buffer list into TXD. Internally created NDIS PACKET
// should always has only one ohysical buffer, and the whole frame size equals
@ -669,10 +644,6 @@ NDIS_STATUS MlmeHardTransmitMgmtRing(
IFS_BACKOFF, FALSE, &pMacEntry->MaxHTPhyMode);
}
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange((PUCHAR)pFirstTxWI, TYPE_TXWI);
#endif
// Now do hardware-depened kick out.
HAL_KickOutMgmtTx(pAd, QueIdx, pPacket, pSrcBufVA, SrcBufLen);
@ -1723,9 +1694,6 @@ BOOLEAN RTMPFreeTXDUponTxDmaDone(
{
PRTMP_TX_RING pTxRing;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
#endif
PNDIS_PACKET pPacket;
UCHAR FREE = 0;
TXD_STRUC TxD, *pOriTxD;
@ -1745,18 +1713,10 @@ BOOLEAN RTMPFreeTXDUponTxDmaDone(
/* Note : If (pAd->ate.bQATxStart == TRUE), we will never reach here. */
FREE++;
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) (pTxRing->Cell[pTxRing->TxSwFreeIdx].AllocVa);
pOriTxD = pTxD;
NdisMoveMemory(&TxD, pTxD, sizeof(TXD_STRUC));
pTxD = &TxD;
#else
pDestTxD = (PTXD_STRUC) (pTxRing->Cell[pTxRing->TxSwFreeIdx].AllocVa);
pOriTxD = pDestTxD ;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#endif
pTxD->DMADONE = 0;
@ -1799,12 +1759,8 @@ BOOLEAN RTMPFreeTXDUponTxDmaDone(
INC_RING_INDEX(pTxRing->TxSwFreeIdx, TX_RING_SIZE);
/* get tx_tdx_idx again */
RTMP_IO_READ32(pAd, TX_DTX_IDX0 + QueIdx * RINGREG_DIFF , &pTxRing->TxDmaIdx);
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
*pDestTxD = TxD;
#else
NdisMoveMemory(pOriTxD, pTxD, sizeof(TXD_STRUC));
#endif
}
@ -1887,10 +1843,6 @@ VOID RTMPHandleMgmtRingDmaDoneInterrupt(
IN PRTMP_ADAPTER pAd)
{
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
PNDIS_PACKET pPacket;
UCHAR FREE = 0;
PRTMP_MGMT_RING pMgmtRing = &pAd->MgmtRing;
@ -1901,14 +1853,7 @@ VOID RTMPHandleMgmtRingDmaDoneInterrupt(
while (pMgmtRing->TxSwFreeIdx!= pMgmtRing->TxDmaIdx)
{
FREE++;
#ifdef RT_BIG_ENDIAN
pDestTxD = (PTXD_STRUC) (pMgmtRing->Cell[pAd->MgmtRing.TxSwFreeIdx].AllocVa);
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#else
pTxD = (PTXD_STRUC) (pMgmtRing->Cell[pAd->MgmtRing.TxSwFreeIdx].AllocVa);
#endif
pTxD->DMADONE = 0;
pPacket = pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNdisPacket;
@ -1928,11 +1873,6 @@ VOID RTMPHandleMgmtRingDmaDoneInterrupt(
}
pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNextNdisPacket = NULL;
INC_RING_INDEX(pMgmtRing->TxSwFreeIdx, MGMT_RING_SIZE);
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, TRUE, TYPE_TXD);
#endif
}
NdisReleaseSpinLock(&pAd->MgmtRingLock);

93
drivers/staging/rt2860/common/cmm_data_2860.c
View File

@ -110,10 +110,6 @@ USHORT RtmpPCI_WriteSingleTxResource(
UCHAR *pDMAHeaderBufVA;
USHORT TxIdx, RetTxIdx;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
UINT32 BufBasePaLow;
PRTMP_TX_RING pTxRing;
USHORT hwHeaderLen;
@ -137,13 +133,8 @@ USHORT RtmpPCI_WriteSingleTxResource(
//
// build Tx Descriptor
//
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
#else
pDestTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
#endif
NdisZeroMemory(pTxD, TXD_SIZE);
pTxD->SDPtr0 = BufBasePaLow;
@ -154,12 +145,6 @@ USHORT RtmpPCI_WriteSingleTxResource(
pTxD->LastSec1 = (bIsLast) ? 1 : 0;
RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange((PUCHAR)(pDMAHeaderBufVA + TXINFO_SIZE), TYPE_TXWI);
RTMPFrameEndianChange(pAd, (PUCHAR)(pDMAHeaderBufVA + TXINFO_SIZE + TXWI_SIZE), DIR_WRITE, FALSE);
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif // RT_BIG_ENDIAN //
RetTxIdx = TxIdx;
//
@ -184,10 +169,6 @@ USHORT RtmpPCI_WriteMultiTxResource(
UCHAR *pDMAHeaderBufVA;
USHORT TxIdx, RetTxIdx;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
UINT32 BufBasePaLow;
PRTMP_TX_RING pTxRing;
USHORT hwHdrLen;
@ -231,13 +212,8 @@ USHORT RtmpPCI_WriteMultiTxResource(
//
// build Tx Descriptor
//
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
#else
pDestTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
#endif
NdisZeroMemory(pTxD, TXD_SIZE);
pTxD->SDPtr0 = BufBasePaLow;
@ -249,17 +225,6 @@ USHORT RtmpPCI_WriteMultiTxResource(
RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
#ifdef RT_BIG_ENDIAN
if (frameNum == 0)
RTMPFrameEndianChange(pAd, (PUCHAR)(pDMAHeaderBufVA+ TXINFO_SIZE + TXWI_SIZE), DIR_WRITE, FALSE);
if (frameNum != 0)
RTMPWIEndianChange((PUCHAR)(pDMAHeaderBufVA + TXINFO_SIZE), TYPE_TXWI);
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif // RT_BIG_ENDIAN //
RetTxIdx = TxIdx;
//
// Update Tx index
@ -290,10 +255,6 @@ VOID RtmpPCI_FinalWriteTxResource(
pTxRing = &pAd->TxRing[pTxBlk->QueIdx];
pTxWI = (PTXWI_STRUC) pTxRing->Cell[FirstTxIdx].DmaBuf.AllocVa;
pTxWI->MPDUtotalByteCount = totalMPDUSize;
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange((PUCHAR)pTxWI, TYPE_TXWI);
#endif // RT_BIG_ENDIAN //
}
@ -303,10 +264,6 @@ VOID RtmpPCIDataLastTxIdx(
IN USHORT LastTxIdx)
{
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
PRTMP_TX_RING pTxRing;
//
@ -317,21 +274,9 @@ VOID RtmpPCIDataLastTxIdx(
//
// build Tx Descriptor
//
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pTxRing->Cell[LastTxIdx].AllocVa;
#else
pDestTxD = (PTXD_STRUC) pTxRing->Cell[LastTxIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
#endif
pTxD->LastSec1 = 1;
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif // RT_BIG_ENDIAN //
}
@ -344,10 +289,6 @@ USHORT RtmpPCI_WriteFragTxResource(
UCHAR *pDMAHeaderBufVA;
USHORT TxIdx, RetTxIdx;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
UINT32 BufBasePaLow;
PRTMP_TX_RING pTxRing;
USHORT hwHeaderLen;
@ -373,13 +314,8 @@ USHORT RtmpPCI_WriteFragTxResource(
//
// Build Tx Descriptor
//
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
#else
pDestTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
#endif
NdisZeroMemory(pTxD, TXD_SIZE);
if (fragNum == pTxBlk->TotalFragNum)
@ -397,13 +333,6 @@ USHORT RtmpPCI_WriteFragTxResource(
RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange((PUCHAR)(pDMAHeaderBufVA + TXINFO_SIZE), TYPE_TXWI);
RTMPFrameEndianChange(pAd, (PUCHAR)(pDMAHeaderBufVA + TXINFO_SIZE + TXWI_SIZE), DIR_WRITE, FALSE);
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif // RT_BIG_ENDIAN //
RetTxIdx = TxIdx;
pTxBlk->Priv += pTxBlk->SrcBufLen;
@ -431,20 +360,9 @@ int RtmpPCIMgmtKickOut(
IN UINT SrcBufLen)
{
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
ULONG SwIdx = pAd->MgmtRing.TxCpuIdx;
#ifdef RT_BIG_ENDIAN
pDestTxD = (PTXD_STRUC)pAd->MgmtRing.Cell[SwIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#else
pTxD = (PTXD_STRUC) pAd->MgmtRing.Cell[SwIdx].AllocVa;
#endif
pAd->MgmtRing.Cell[SwIdx].pNdisPacket = pPacket;
pAd->MgmtRing.Cell[SwIdx].pNextNdisPacket = NULL;
@ -457,11 +375,6 @@ int RtmpPCIMgmtKickOut(
pTxD->SDPtr0 = PCI_MAP_SINGLE(pAd, pSrcBufVA, SrcBufLen, 0, PCI_DMA_TODEVICE);;
pTxD->SDLen0 = SrcBufLen;
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif
pAd->RalinkCounters.KickTxCount++;
pAd->RalinkCounters.OneSecTxDoneCount++;

27
drivers/staging/rt2860/common/cmm_sync.c
View File

@ -582,52 +582,27 @@ VOID ScanNextChannel(
ULONG Tmp;
UCHAR HtLen;
UCHAR BROADCOM[4] = {0x0, 0x90, 0x4c, 0x33};
#ifdef RT_BIG_ENDIAN
HT_CAPABILITY_IE HtCapabilityTmp;
#endif
if (pAd->bBroadComHT == TRUE)
{
HtLen = pAd->MlmeAux.HtCapabilityLen + 4;
#ifdef RT_BIG_ENDIAN
NdisMoveMemory(&HtCapabilityTmp, &pAd->MlmeAux.HtCapability, SIZE_HT_CAP_IE);
*(USHORT *)(&HtCapabilityTmp.HtCapInfo) = SWAP16(*(USHORT *)(&HtCapabilityTmp.HtCapInfo));
*(USHORT *)(&HtCapabilityTmp.ExtHtCapInfo) = SWAP16(*(USHORT *)(&HtCapabilityTmp.ExtHtCapInfo));
MakeOutgoingFrame(pOutBuffer + FrameLen, &Tmp,
1, &WpaIe,
1, &HtLen,
4, &BROADCOM[0],
pAd->MlmeAux.HtCapabilityLen, &HtCapabilityTmp,
END_OF_ARGS);
#else
MakeOutgoingFrame(pOutBuffer + FrameLen, &Tmp,
1, &WpaIe,
1, &HtLen,
4, &BROADCOM[0],
pAd->MlmeAux.HtCapabilityLen, &pAd->MlmeAux.HtCapability,
END_OF_ARGS);
#endif // RT_BIG_ENDIAN //
}
else
{
HtLen = pAd->MlmeAux.HtCapabilityLen;
#ifdef RT_BIG_ENDIAN
NdisMoveMemory(&HtCapabilityTmp, &pAd->CommonCfg.HtCapability, SIZE_HT_CAP_IE);
*(USHORT *)(&HtCapabilityTmp.HtCapInfo) = SWAP16(*(USHORT *)(&HtCapabilityTmp.HtCapInfo));
*(USHORT *)(&HtCapabilityTmp.ExtHtCapInfo) = SWAP16(*(USHORT *)(&HtCapabilityTmp.ExtHtCapInfo));
MakeOutgoingFrame(pOutBuffer + FrameLen, &Tmp,
1, &HtCapIe,
1, &HtLen,
HtLen, &HtCapabilityTmp,
END_OF_ARGS);
#else
MakeOutgoingFrame(pOutBuffer + FrameLen, &Tmp,
1, &HtCapIe,
1, &HtLen,
HtLen, &pAd->CommonCfg.HtCapability,
END_OF_ARGS);
#endif // RT_BIG_ENDIAN //
}
FrameLen += Tmp;
}

12
drivers/staging/rt2860/common/md5.c
View File

@ -131,19 +131,7 @@ void hmac_md5(u8 *key, size_t key_len, u8 *data, size_t data_len, u8 *mac)
MD5Final(mac, &context); /* finish up 2nd pass */
}
#ifndef RT_BIG_ENDIAN
#define byteReverse(buf, len) /* Nothing */
#else
void byteReverse(unsigned char *buf, unsigned longs);
void byteReverse(unsigned char *buf, unsigned longs)
{
do {
*(UINT32 *)buf = SWAP32(*(UINT32 *)buf);
buf += 4;
} while (--longs);
}
#endif
/* ========================== MD5 implementation =========================== */
// four base functions for MD5

21
drivers/staging/rt2860/common/rtmp_tkip.c
View File

@ -199,15 +199,9 @@ typedef struct PACKED _IV_CONTROL_
{
struct PACKED
{
#ifdef RT_BIG_ENDIAN
UCHAR KeyID:2;
UCHAR ExtIV:1;
UCHAR Rsvd:5;
#else
UCHAR Rsvd:5;
UCHAR ExtIV:1;
UCHAR KeyID:2;
#endif
} field;
UCHAR Byte;
} CONTROL;
@ -1114,10 +1108,6 @@ BOOLEAN RTMPSoftDecryptTKIP(
UCHAR MIC[8];
UCHAR TrailMIC[8];
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (PUCHAR)pData, DIR_READ, FALSE);
#endif
fc0 = *pData;
fc1 = *(pData + 1);
@ -1224,9 +1214,6 @@ BOOLEAN RTMPSoftDecryptTKIP(
return (FALSE);
}
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (PUCHAR)pData, DIR_READ, FALSE);
#endif
return TRUE;
}
@ -1266,10 +1253,6 @@ BOOLEAN RTMPSoftDecryptAES(
UCHAR MIC[8];
UCHAR TrailMIC[8];
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (PUCHAR)pData, DIR_READ, FALSE);
#endif
fc0 = *pData;
fc1 = *(pData + 1);
@ -1437,10 +1420,6 @@ BOOLEAN RTMPSoftDecryptAES(
return FALSE;
}
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (PUCHAR)pData, DIR_READ, FALSE);
#endif
return TRUE;
}

260
drivers/staging/rt2860/mlme.h
View File

@ -196,22 +196,6 @@ if (((__pEntry)) != NULL) \
//
// HT Capability INFO field in HT Cap IE .
typedef struct PACKED {
#ifdef RT_BIG_ENDIAN
USHORT LSIGTxopProSup:1;
USHORT Forty_Mhz_Intolerant:1;
USHORT PSMP:1;
USHORT CCKmodein40:1;
USHORT AMsduSize:1;
USHORT DelayedBA:1; //rt2860c not support
USHORT RxSTBC:2;
USHORT TxSTBC:1;
USHORT ShortGIfor40:1; //for40MHz
USHORT ShortGIfor20:1;
USHORT GF:1; //green field
USHORT MimoPs:2;//momi power safe
USHORT ChannelWidth:1;
USHORT AdvCoding:1;
#else
USHORT AdvCoding:1;
USHORT ChannelWidth:1;
USHORT MimoPs:2;//momi power safe
@ -226,53 +210,29 @@ typedef struct PACKED {
USHORT PSMP:1;
USHORT Forty_Mhz_Intolerant:1;
USHORT LSIGTxopProSup:1;
#endif /* !RT_BIG_ENDIAN */
} HT_CAP_INFO, *PHT_CAP_INFO;
// HT Capability INFO field in HT Cap IE .
typedef struct PACKED {
#ifdef RT_BIG_ENDIAN
UCHAR rsv:3;//momi power safe
UCHAR MpduDensity:3;
UCHAR MaxRAmpduFactor:2;
#else
UCHAR MaxRAmpduFactor:2;
UCHAR MpduDensity:3;
UCHAR rsv:3;//momi power safe
#endif /* !RT_BIG_ENDIAN */
} HT_CAP_PARM, *PHT_CAP_PARM;
// HT Capability INFO field in HT Cap IE .
typedef struct PACKED {
UCHAR MCSSet[10];
UCHAR SupRate[2]; // unit : 1Mbps
#ifdef RT_BIG_ENDIAN
UCHAR rsv:3;
UCHAR MpduDensity:1;
UCHAR TxStream:2;
UCHAR TxRxNotEqual:1;
UCHAR TxMCSSetDefined:1;
#else
UCHAR TxMCSSetDefined:1;
UCHAR TxRxNotEqual:1;
UCHAR TxStream:2;
UCHAR MpduDensity:1;
UCHAR rsv:3;
#endif // RT_BIG_ENDIAN //
UCHAR rsv3[3];
} HT_MCS_SET, *PHT_MCS_SET;
// HT Capability INFO field in HT Cap IE .
typedef struct PACKED {
#ifdef RT_BIG_ENDIAN
USHORT rsv2:4;
USHORT RDGSupport:1; //reverse Direction Grant support
USHORT PlusHTC:1; //+HTC control field support
USHORT MCSFeedback:2; //0:no MCS feedback, 2:unsolicited MCS feedback, 3:Full MCS feedback, 1:rsv.
USHORT rsv:5;//momi power safe
USHORT TranTime:2;
USHORT Pco:1;
#else
USHORT Pco:1;
USHORT TranTime:2;
USHORT rsv:5;//momi power safe
@ -280,33 +240,10 @@ typedef struct PACKED {
USHORT PlusHTC:1; //+HTC control field support
USHORT RDGSupport:1; //reverse Direction Grant support
USHORT rsv2:4;
#endif /* RT_BIG_ENDIAN */
} EXT_HT_CAP_INFO, *PEXT_HT_CAP_INFO;
// HT Beamforming field in HT Cap IE .
typedef struct PACKED _HT_BF_CAP{
#ifdef RT_BIG_ENDIAN
ULONG rsv:3;
ULONG ChanEstimation:2;
ULONG CSIRowBFSup:2;
ULONG ComSteerBFAntSup:2;
ULONG NoComSteerBFAntSup:2;
ULONG CSIBFAntSup:2;
ULONG MinGrouping:2;
ULONG ExpComBF:2;
ULONG ExpNoComBF:2;
ULONG ExpCSIFbk:2;
ULONG ExpComSteerCapable:1;
ULONG ExpNoComSteerCapable:1;
ULONG ExpCSICapable:1;
ULONG Calibration:2;
ULONG ImpTxBFCapable:1;
ULONG TxNDPCapable:1;
ULONG RxNDPCapable:1;
ULONG TxSoundCapable:1;
ULONG RxSoundCapable:1;
ULONG TxBFRecCapable:1;
#else
ULONG TxBFRecCapable:1;
ULONG RxSoundCapable:1;
ULONG TxSoundCapable:1;
@ -327,21 +264,10 @@ typedef struct PACKED _HT_BF_CAP{
ULONG CSIRowBFSup:2;
ULONG ChanEstimation:2;
ULONG rsv:3;
#endif // RT_BIG_ENDIAN //
} HT_BF_CAP, *PHT_BF_CAP;
// HT antenna selection field in HT Cap IE .
typedef struct PACKED _HT_AS_CAP{
#ifdef RT_BIG_ENDIAN
UCHAR rsv:1;
UCHAR TxSoundPPDU:1;
UCHAR RxASel:1;
UCHAR AntIndFbk:1;
UCHAR ExpCSIFbk:1;
UCHAR AntIndFbkTxASEL:1;
UCHAR ExpCSIFbkTxASEL:1;
UCHAR AntSelect:1;
#else
UCHAR AntSelect:1;
UCHAR ExpCSIFbkTxASEL:1;
UCHAR AntIndFbkTxASEL:1;
@ -350,7 +276,6 @@ typedef struct PACKED _HT_AS_CAP{
UCHAR RxASel:1;
UCHAR TxSoundPPDU:1;
UCHAR rsv:1;
#endif // RT_BIG_ENDIAN //
} HT_AS_CAP, *PHT_AS_CAP;
// Draft 1.0 set IE length 26, but is extensible..
@ -394,17 +319,10 @@ typedef struct PACKED _OVERLAP_BSS_SCAN_IE{
// 7.3.2.56. 20/40 Coexistence element used in Element ID = 72 = IE_2040_BSS_COEXIST
typedef union PACKED _BSS_2040_COEXIST_IE{
struct PACKED {
#ifdef RT_BIG_ENDIAN
UCHAR rsv:5;
UCHAR BSS20WidthReq:1;
UCHAR Intolerant40:1;
UCHAR InfoReq:1;
#else
UCHAR InfoReq:1;
UCHAR Intolerant40:1; // Inter-BSS. set 1 when prohibits a receiving BSS from operating as a 20/40 Mhz BSS.
UCHAR BSS20WidthReq:1; // Intra-BSS set 1 when prohibits a receiving AP from operating its BSS as a 20/40MHz BSS.
UCHAR rsv:5;
#endif // RT_BIG_ENDIAN //
} field;
UCHAR word;
} BSS_2040_COEXIST_IE, *PBSS_2040_COEXIST_IE;
@ -430,17 +348,10 @@ typedef struct _TRIGGER_EVENT_TAB{
// 7.3.27 20/40 Bss Coexistence Mgmt capability used in extended capabilities information IE( ID = 127 = IE_EXT_CAPABILITY).
// This is the first octet and was defined in 802.11n D3.03 and 802.11yD9.0
typedef struct PACKED _EXT_CAP_INFO_ELEMENT{
#ifdef RT_BIG_ENDIAN
UCHAR rsv2:5;
UCHAR ExtendChannelSwitch:1;
UCHAR rsv:1;
UCHAR BssCoexistMgmtSupport:1;
#else
UCHAR BssCoexistMgmtSupport:1;
UCHAR rsv:1;
UCHAR ExtendChannelSwitch:1;
UCHAR rsv2:5;
#endif // RT_BIG_ENDIAN //
}EXT_CAP_INFO_ELEMENT, *PEXT_CAP_INFO_ELEMENT;
@ -486,18 +397,6 @@ typedef struct {
//This structure substracts ralink supports from all 802.11n-related features.
//Features not listed here but contained in 802.11n spec are not supported in rt2860.
typedef struct {
#ifdef RT_BIG_ENDIAN
USHORT rsv:5;
USHORT AmsduSize:1; // Max receiving A-MSDU size
USHORT AmsduEnable:1; // Enable to transmit A-MSDU. Suggest disable. We should use A-MPDU to gain best benifit of 802.11n
USHORT RxSTBC:2; // 2 bits
USHORT TxSTBC:1;
USHORT ShortGIfor40:1; //for40MHz
USHORT ShortGIfor20:1;
USHORT GF:1; //green field
USHORT MimoPs:2;//mimo power safe MMPS_
USHORT ChannelWidth:1;
#else
USHORT ChannelWidth:1;
USHORT MimoPs:2;//mimo power safe MMPS_
USHORT GF:1; //green field
@ -508,34 +407,18 @@ typedef struct {
USHORT AmsduEnable:1; // Enable to transmit A-MSDU. Suggest disable. We should use A-MPDU to gain best benifit of 802.11n
USHORT AmsduSize:1; // Max receiving A-MSDU size
USHORT rsv:5;
#endif
//Substract from Addiont HT INFO IE
#ifdef RT_BIG_ENDIAN
UCHAR RecomWidth:1;
UCHAR ExtChanOffset:2; // Please not the difference with following UCHAR NewExtChannelOffset; from 802.11n
UCHAR MpduDensity:3;
UCHAR MaxRAmpduFactor:2;
#else
UCHAR MaxRAmpduFactor:2;
UCHAR MpduDensity:3;
UCHAR ExtChanOffset:2; // Please not the difference with following UCHAR NewExtChannelOffset; from 802.11n
UCHAR RecomWidth:1;
#endif
#ifdef RT_BIG_ENDIAN
USHORT rsv2:11;
USHORT OBSS_NonHTExist:1;
USHORT rsv3:1;
USHORT NonGfPresent:1;
USHORT OperaionMode:2;
#else
USHORT OperaionMode:2;
USHORT NonGfPresent:1;
USHORT rsv3:1;
USHORT OBSS_NonHTExist:1;
USHORT rsv2:11;
#endif
// New Extension Channel Offset IE
UCHAR NewExtChannelOffset;
@ -545,50 +428,24 @@ typedef struct {
// field in Addtional HT Information IE .
typedef struct PACKED {
#ifdef RT_BIG_ENDIAN
UCHAR SerInterGranu:3;
UCHAR S_PSMPSup:1;
UCHAR RifsMode:1;
UCHAR RecomWidth:1;
UCHAR ExtChanOffset:2;
#else
UCHAR ExtChanOffset:2;
UCHAR RecomWidth:1;
UCHAR RifsMode:1;
UCHAR S_PSMPSup:1; //Indicate support for scheduled PSMP
UCHAR SerInterGranu:3; //service interval granularity
#endif
} ADD_HTINFO, *PADD_HTINFO;
typedef struct PACKED{
#ifdef RT_BIG_ENDIAN
USHORT rsv2:11;
USHORT OBSS_NonHTExist:1;
USHORT rsv:1;
USHORT NonGfPresent:1;
USHORT OperaionMode:2;
#else
USHORT OperaionMode:2;
USHORT NonGfPresent:1;
USHORT rsv:1;
USHORT OBSS_NonHTExist:1;
USHORT rsv2:11;
#endif
} ADD_HTINFO2, *PADD_HTINFO2;
// TODO: Need sync with spec about the definition of StbcMcs. In Draft 3.03, it's reserved.
typedef struct PACKED{
#ifdef RT_BIG_ENDIAN
USHORT rsv:4;
USHORT PcoPhase:1;
USHORT PcoActive:1;
USHORT LsigTxopProt:1;
USHORT STBCBeacon:1;
USHORT DualCTSProtect:1;
USHORT DualBeacon:1;
USHORT StbcMcs:6;
#else
USHORT StbcMcs:6;
USHORT DualBeacon:1;
USHORT DualCTSProtect:1;
@ -597,7 +454,6 @@ typedef struct PACKED{
USHORT PcoActive:1;
USHORT PcoPhase:1;
USHORT rsv:4;
#endif // RT_BIG_ENDIAN //
} ADD_HTINFO3, *PADD_HTINFO3;
#define SIZE_ADD_HT_INFO_IE 22
@ -616,22 +472,6 @@ typedef struct PACKED{
// 4-byte HTC field. maybe included in any frame except non-QOS data frame. The Order bit must set 1.
typedef struct PACKED {
#ifdef RT_BIG_ENDIAN
UINT32 RDG:1; //RDG / More PPDU
UINT32 ACConstraint:1; //feedback request
UINT32 rsv:5; //calibration sequence
UINT32 ZLFAnnouce:1; // ZLF announcement
UINT32 CSISTEERING:2; //CSI/ STEERING
UINT32 FBKReq:2; //feedback request
UINT32 CalSeq:2; //calibration sequence
UINT32 CalPos:2; // calibration position
UINT32 MFBorASC:7; //Link adaptation feedback containing recommended MCS. 0x7f for no feedback or not available
UINT32 MFS:3; //SET to the received value of MRS. 0x111 for unsolicited MFB.
UINT32 MRSorASI:3; // MRQ Sequence identifier. unchanged during entire procedure. 0x000-0x110.
UINT32 MRQ:1; //MCS feedback. Request for a MCS feedback
UINT32 TRQ:1; //sounding request
UINT32 MA:1; //management action payload exist in (QoS Null+HTC)
#else
UINT32 MA:1; //management action payload exist in (QoS Null+HTC)
UINT32 TRQ:1; //sounding request
UINT32 MRQ:1; //MCS feedback. Request for a MCS feedback
@ -646,41 +486,19 @@ typedef struct PACKED {
UINT32 rsv:5; //calibration sequence
UINT32 ACConstraint:1; //feedback request
UINT32 RDG:1; //RDG / More PPDU
#endif /* !RT_BIG_ENDIAN */
} HT_CONTROL, *PHT_CONTROL;
// 2-byte QOS CONTROL field
typedef struct PACKED {
#ifdef RT_BIG_ENDIAN
USHORT Txop_QueueSize:8;
USHORT AMsduPresent:1;
USHORT AckPolicy:2; //0: normal ACK 1:No ACK 2:scheduled under MTBA/PSMP 3: BA
USHORT EOSP:1;
USHORT TID:4;
#else
USHORT TID:4;
USHORT EOSP:1;
USHORT AckPolicy:2; //0: normal ACK 1:No ACK 2:scheduled under MTBA/PSMP 3: BA
USHORT AMsduPresent:1;
USHORT Txop_QueueSize:8;
#endif /* !RT_BIG_ENDIAN */
} QOS_CONTROL, *PQOS_CONTROL;
// 2-byte Frame control field
typedef struct PACKED {
#ifdef RT_BIG_ENDIAN
USHORT Order:1; // Strict order expected
USHORT Wep:1; // Wep data
USHORT MoreData:1; // More data bit
USHORT PwrMgmt:1; // Power management bit
USHORT Retry:1; // Retry status bit
USHORT MoreFrag:1; // More fragment bit
USHORT FrDs:1; // From DS indication
USHORT ToDs:1; // To DS indication
USHORT SubType:4; // MSDU subtype
USHORT Type:2; // MSDU type
USHORT Ver:2; // Protocol version
#else
USHORT Ver:2; // Protocol version
USHORT Type:2; // MSDU type
USHORT SubType:4; // MSDU subtype
@ -692,7 +510,6 @@ typedef struct PACKED {
USHORT MoreData:1; // More data bit
USHORT Wep:1; // Wep data
USHORT Order:1; // Strict order expected
#endif /* !RT_BIG_ENDIAN */
} FRAME_CONTROL, *PFRAME_CONTROL;
typedef struct PACKED _HEADER_802_11 {
@ -701,13 +518,8 @@ typedef struct PACKED _HEADER_802_11 {
UCHAR Addr1[MAC_ADDR_LEN];
UCHAR Addr2[MAC_ADDR_LEN];
UCHAR Addr3[MAC_ADDR_LEN];
#ifdef RT_BIG_ENDIAN
USHORT Sequence:12;
USHORT Frag:4;
#else
USHORT Frag:4;
USHORT Sequence:12;
#endif /* !RT_BIG_ENDIAN */
UCHAR Octet[0];
} HEADER_802_11, *PHEADER_802_11;
@ -731,42 +543,24 @@ typedef struct PACKED _HEADER_802_3 {
////Block ACK related format
// 2-byte BA Parameter field in DELBA frames to terminate an already set up bA
typedef struct PACKED{
#ifdef RT_BIG_ENDIAN
USHORT TID:4; // value of TC os TS
USHORT Initiator:1; // 1: originator 0:recipient
USHORT Rsv:11; // always set to 0
#else
USHORT Rsv:11; // always set to 0
USHORT Initiator:1; // 1: originator 0:recipient
USHORT TID:4; // value of TC os TS
#endif /* !RT_BIG_ENDIAN */
} DELBA_PARM, *PDELBA_PARM;
// 2-byte BA Parameter Set field in ADDBA frames to signal parm for setting up a BA
typedef struct PACKED {
#ifdef RT_BIG_ENDIAN
USHORT BufSize:10; // number of buffe of size 2304 octetsr
USHORT TID:4; // value of TC os TS
USHORT BAPolicy:1; // 1: immediately BA 0:delayed BA
USHORT AMSDUSupported:1; // 0: not permitted 1: permitted
#else
USHORT AMSDUSupported:1; // 0: not permitted 1: permitted
USHORT BAPolicy:1; // 1: immediately BA 0:delayed BA
USHORT TID:4; // value of TC os TS
USHORT BufSize:10; // number of buffe of size 2304 octetsr
#endif /* !RT_BIG_ENDIAN */
} BA_PARM, *PBA_PARM;
// 2-byte BA Starting Seq CONTROL field
typedef union PACKED {
struct PACKED {
#ifdef RT_BIG_ENDIAN
USHORT StartSeq:12; // sequence number of the 1st MSDU for which this BAR is sent
USHORT FragNum:4; // always set to 0
#else
USHORT FragNum:4; // always set to 0
USHORT StartSeq:12; // sequence number of the 1st MSDU for which this BAR is sent
#endif /* RT_BIG_ENDIAN */
} field;
USHORT word;
} BASEQ_CONTROL, *PBASEQ_CONTROL;
@ -774,63 +568,34 @@ typedef union PACKED {
//BAControl and BARControl are the same
// 2-byte BA CONTROL field in BA frame
typedef struct PACKED {
#ifdef RT_BIG_ENDIAN
USHORT TID:4;
USHORT Rsv:9;
USHORT Compressed:1;
USHORT MTID:1; //EWC V1.24
USHORT ACKPolicy:1; // only related to N-Delayed BA. But not support in RT2860b. 0:NormalACK 1:No ACK
#else
USHORT ACKPolicy:1; // only related to N-Delayed BA. But not support in RT2860b. 0:NormalACK 1:No ACK
USHORT MTID:1; //EWC V1.24
USHORT Compressed:1;
USHORT Rsv:9;
USHORT TID:4;
#endif /* !RT_BIG_ENDIAN */
} BA_CONTROL, *PBA_CONTROL;
// 2-byte BAR CONTROL field in BAR frame
typedef struct PACKED {
#ifdef RT_BIG_ENDIAN
USHORT TID:4;
USHORT Rsv1:9;
USHORT Compressed:1;
USHORT MTID:1; //if this bit1, use FRAME_MTBA_REQ, if 0, use FRAME_BA_REQ
USHORT ACKPolicy:1;
#else
USHORT ACKPolicy:1; // 0:normal ack, 1:no ack.
USHORT MTID:1; //if this bit1, use FRAME_MTBA_REQ, if 0, use FRAME_BA_REQ
USHORT Compressed:1;
USHORT Rsv1:9;
USHORT TID:4;
#endif /* !RT_BIG_ENDIAN */
} BAR_CONTROL, *PBAR_CONTROL;
// BARControl in MTBAR frame
typedef struct PACKED {
#ifdef RT_BIG_ENDIAN
USHORT NumTID:4;
USHORT Rsv1:9;
USHORT Compressed:1;
USHORT MTID:1;
USHORT ACKPolicy:1;
#else
USHORT ACKPolicy:1;
USHORT MTID:1;
USHORT Compressed:1;
USHORT Rsv1:9;
USHORT NumTID:4;
#endif /* !RT_BIG_ENDIAN */
} MTBAR_CONTROL, *PMTBAR_CONTROL;
typedef struct PACKED {
#ifdef RT_BIG_ENDIAN
USHORT TID:4;
USHORT Rsv1:12;
#else
USHORT Rsv1:12;
USHORT TID:4;
#endif /* !RT_BIG_ENDIAN */
} PER_TID_INFO, *PPER_TID_INFO;
typedef struct {
@ -1050,15 +815,6 @@ typedef struct {
// QBSS Info field in QSTA's assoc req
typedef struct PACKED {
#ifdef RT_BIG_ENDIAN
UCHAR Rsv2:1;
UCHAR MaxSPLength:2;
UCHAR Rsv1:1;
UCHAR UAPSD_AC_BE:1;
UCHAR UAPSD_AC_BK:1;
UCHAR UAPSD_AC_VI:1;
UCHAR UAPSD_AC_VO:1;
#else
UCHAR UAPSD_AC_VO:1;
UCHAR UAPSD_AC_VI:1;
UCHAR UAPSD_AC_BK:1;
@ -1066,20 +822,13 @@ typedef struct PACKED {
UCHAR Rsv1:1;
UCHAR MaxSPLength:2;
UCHAR Rsv2:1;
#endif /* !RT_BIG_ENDIAN */
} QBSS_STA_INFO_PARM, *PQBSS_STA_INFO_PARM;
// QBSS Info field in QAP's Beacon/ProbeRsp
typedef struct PACKED {
#ifdef RT_BIG_ENDIAN
UCHAR UAPSD:1;
UCHAR Rsv:3;
UCHAR ParamSetCount:4;
#else
UCHAR ParamSetCount:4;
UCHAR Rsv:3;
UCHAR UAPSD:1;
#endif /* !RT_BIG_ENDIAN */
} QBSS_AP_INFO_PARM, *PQBSS_AP_INFO_PARM;
// QOS Capability reported in QAP's BEACON/ProbeRsp
@ -1330,21 +1079,12 @@ typedef struct PACKED {
typedef struct PACKED _RTMP_TX_RATE_SWITCH
{
UCHAR ItemNo;
#ifdef RT_BIG_ENDIAN
UCHAR Rsv2:2;
UCHAR Mode:2;
UCHAR Rsv1:1;
UCHAR BW:1;
UCHAR ShortGI:1;
UCHAR STBC:1;
#else
UCHAR STBC:1;
UCHAR ShortGI:1;
UCHAR BW:1;
UCHAR Rsv1:1;
UCHAR Mode:2;
UCHAR Rsv2:2;
#endif
UCHAR CurrMCS;
UCHAR TrainUp;
UCHAR TrainDown;

12
drivers/staging/rt2860/oid.h
View File

@ -682,17 +682,6 @@ enum {
// MIMO Tx parameter, ShortGI, MCS, STBC, etc. these are fields in TXWI. Don't change this definition!!!
typedef union _HTTRANSMIT_SETTING {
#ifdef RT_BIG_ENDIAN
struct {
USHORT MODE:2; // Use definition MODE_xxx.
USHORT TxBF:1;
USHORT rsv:2;
USHORT STBC:2; //SPACE
USHORT ShortGI:1;
USHORT BW:1; //channel bandwidth 20MHz or 40 MHz
USHORT MCS:7; // MCS
} field;
#else
struct {
USHORT MCS:7; // MCS
USHORT BW:1; //channel bandwidth 20MHz or 40 MHz
@ -702,7 +691,6 @@ typedef union _HTTRANSMIT_SETTING {
USHORT TxBF:1;
USHORT MODE:2; // Use definition MODE_xxx.
} field;
#endif
USHORT word;
} HTTRANSMIT_SETTING, *PHTTRANSMIT_SETTING;

1191
drivers/staging/rt2860/rt28xx.h
View File

File diff suppressed because it is too large Load Diff

293
drivers/staging/rt2860/rtmp.h
View File

@ -889,17 +889,10 @@ typedef struct _RTMP_DMABUF
typedef union _HEADER_802_11_SEQ{
#ifdef RT_BIG_ENDIAN
struct {
USHORT Sequence:12;
USHORT Frag:4;
} field;
#else
struct {
USHORT Frag:4;
USHORT Sequence:12;
} field;
#endif
USHORT value;
} HEADER_802_11_SEQ, *PHEADER_802_11_SEQ;
@ -1111,15 +1104,6 @@ typedef struct _ARCFOUR
// MIMO Tx parameter, ShortGI, MCS, STBC, etc. these are fields in TXWI too. just copy to TXWI.
typedef struct _RECEIVE_SETTING {
#ifdef RT_BIG_ENDIAN
USHORT MIMO:1;
USHORT OFDM:1;
USHORT rsv:3;
USHORT STBC:2; //SPACE
USHORT ShortGI:1;
USHORT Mode:2; //channel bandwidth 20MHz or 40 MHz
USHORT NumOfRX:2; // MIMO. WE HAVE 3R
#else
USHORT NumOfRX:2; // MIMO. WE HAVE 3R
USHORT Mode:2; //channel bandwidth 20MHz or 40 MHz
USHORT ShortGI:1;
@ -1127,7 +1111,6 @@ typedef struct _RECEIVE_SETTING {
USHORT rsv:3;
USHORT OFDM:1;
USHORT MIMO:1;
#endif
} RECEIVE_SETTING, *PRECEIVE_SETTING;
// Shared key data structure
@ -1453,21 +1436,6 @@ typedef struct _QUERYBA_TABLE{
} QUERYBA_TABLE, *PQUERYBA_TABLE;
typedef union _BACAP_STRUC {
#ifdef RT_BIG_ENDIAN
struct {
UINT32 :4;
UINT32 b2040CoexistScanSup:1; //As Sta, support do 2040 coexistence scan for AP. As Ap, support monitor trigger event to check if can use BW 40MHz.
UINT32 bHtAdhoc:1; // adhoc can use ht rate.
UINT32 MMPSmode:2; // MIMO power save more, 0:static, 1:dynamic, 2:rsv, 3:mimo enable
UINT32 AmsduSize:1; // 0:3839, 1:7935 bytes. UINT MSDUSizeToBytes[] = { 3839, 7935};
UINT32 AmsduEnable:1; //Enable AMSDU transmisstion
UINT32 MpduDensity:3;
UINT32 Policy:2; // 0: DELAY_BA 1:IMMED_BA (//BA Policy subfiled value in ADDBA frame) 2:BA-not use
UINT32 AutoBA:1; // automatically BA
UINT32 TxBAWinLimit:8;
UINT32 RxBAWinLimit:8;
} field;
#else
struct {
UINT32 RxBAWinLimit:8;
UINT32 TxBAWinLimit:8;
@ -1481,7 +1449,6 @@ typedef union _BACAP_STRUC {
UINT32 b2040CoexistScanSup:1; //As Sta, support do 2040 coexistence scan for AP. As Ap, support monitor trigger event to check if can use BW 40MHz.
UINT32 :4;
} field;
#endif
UINT32 word;
} BACAP_STRUC, *PBACAP_STRUC;
#endif // DOT11_N_SUPPORT //
@ -1510,19 +1477,6 @@ typedef struct _IOT_STRUC {
// This is the registry setting for 802.11n transmit setting. Used in advanced page.
typedef union _REG_TRANSMIT_SETTING {
#ifdef RT_BIG_ENDIAN
struct {
UINT32 rsv:13;
UINT32 EXTCHA:2;
UINT32 HTMODE:1;
UINT32 TRANSNO:2;
UINT32 STBC:1; //SPACE
UINT32 ShortGI:1;
UINT32 BW:1; //channel bandwidth 20MHz or 40 MHz
UINT32 TxBF:1; // 3*3
UINT32 rsv0:10;
} field;
#else
struct {
UINT32 rsv0:10;
UINT32 TxBF:1;
@ -1534,26 +1488,16 @@ typedef union _REG_TRANSMIT_SETTING {
UINT32 EXTCHA:2;
UINT32 rsv:13;
} field;
#endif
UINT32 word;
} REG_TRANSMIT_SETTING, *PREG_TRANSMIT_SETTING;
typedef union _DESIRED_TRANSMIT_SETTING {
#ifdef RT_BIG_ENDIAN
struct {
USHORT rsv:3;
USHORT FixedTxMode:2; // If MCS isn't AUTO, fix rate in CCK, OFDM or HT mode.
USHORT PhyMode:4;
USHORT MCS:7; // MCS
} field;
#else
struct {
USHORT MCS:7; // MCS
USHORT PhyMode:4;
USHORT FixedTxMode:2; // If MCS isn't AUTO, fix rate in CCK, OFDM or HT mode.
USHORT rsv:3;
} field;
#endif
USHORT word;
} DESIRED_TRANSMIT_SETTING, *PDESIRED_TRANSMIT_SETTING;
@ -2966,243 +2910,6 @@ __inline VOID NICEnableInterrupt(
RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_ACTIVE);
}
#ifdef RT_BIG_ENDIAN
static inline VOID WriteBackToDescriptor(
IN PUCHAR Dest,
IN PUCHAR Src,
IN BOOLEAN DoEncrypt,
IN ULONG DescriptorType)
{
UINT32 *p1, *p2;
p1 = ((UINT32 *)Dest);
p2 = ((UINT32 *)Src);
*p1 = *p2;
*(p1+2) = *(p2+2);
*(p1+3) = *(p2+3);
*(p1+1) = *(p2+1); // Word 1; this must be written back last
}
/*
========================================================================
Routine Description:
Endian conversion of Tx/Rx descriptor .
Arguments:
pAd Pointer to our adapter
pData Pointer to Tx/Rx descriptor
DescriptorType Direction of the frame
Return Value:
None
Note:
Call this function when read or update descriptor
========================================================================
*/
static inline VOID RTMPWIEndianChange(
IN PUCHAR pData,
IN ULONG DescriptorType)
{
int size;
int i;
size = ((DescriptorType == TYPE_TXWI) ? TXWI_SIZE : RXWI_SIZE);
if(DescriptorType == TYPE_TXWI)
{
*((UINT32 *)(pData)) = SWAP32(*((UINT32 *)(pData))); // Byte 0~3
*((UINT32 *)(pData + 4)) = SWAP32(*((UINT32 *)(pData+4))); // Byte 4~7
}
else
{
for(i=0; i < size/4 ; i++)
*(((UINT32 *)pData) +i) = SWAP32(*(((UINT32 *)pData)+i));
}
}
/*
========================================================================
Routine Description:
Endian conversion of Tx/Rx descriptor .
Arguments:
pAd Pointer to our adapter
pData Pointer to Tx/Rx descriptor
DescriptorType Direction of the frame
Return Value:
None
Note:
Call this function when read or update descriptor
========================================================================
*/
static inline VOID RTMPDescriptorEndianChange(
IN PUCHAR pData,
IN ULONG DescriptorType)
{
*((UINT32 *)(pData)) = SWAP32(*((UINT32 *)(pData))); // Byte 0~3
*((UINT32 *)(pData + 8)) = SWAP32(*((UINT32 *)(pData+8))); // Byte 8~11
*((UINT32 *)(pData +12)) = SWAP32(*((UINT32 *)(pData + 12))); // Byte 12~15
*((UINT32 *)(pData + 4)) = SWAP32(*((UINT32 *)(pData + 4))); // Byte 4~7, this must be swapped last
}
/*
========================================================================
Routine Description:
Endian conversion of all kinds of 802.11 frames .
Arguments:
pAd Pointer to our adapter
pData Pointer to the 802.11 frame structure
Dir Direction of the frame
FromRxDoneInt Caller is from RxDone interrupt
Return Value:
None
Note:
Call this function when read or update buffer data
========================================================================
*/
static inline VOID RTMPFrameEndianChange(
IN PRTMP_ADAPTER pAd,
IN PUCHAR pData,
IN ULONG Dir,
IN BOOLEAN FromRxDoneInt)
{
PHEADER_802_11 pFrame;
PUCHAR pMacHdr;
// swab 16 bit fields - Frame Control field
if(Dir == DIR_READ)
{
*(USHORT *)pData = SWAP16(*(USHORT *)pData);
}
pFrame = (PHEADER_802_11) pData;
pMacHdr = (PUCHAR) pFrame;
// swab 16 bit fields - Duration/ID field
*(USHORT *)(pMacHdr + 2) = SWAP16(*(USHORT *)(pMacHdr + 2));
// swab 16 bit fields - Sequence Control field
*(USHORT *)(pMacHdr + 22) = SWAP16(*(USHORT *)(pMacHdr + 22));
if(pFrame->FC.Type == BTYPE_MGMT)
{
switch(pFrame->FC.SubType)
{
case SUBTYPE_ASSOC_REQ:
case SUBTYPE_REASSOC_REQ:
// swab 16 bit fields - CapabilityInfo field
pMacHdr += sizeof(HEADER_802_11);
*(USHORT *)pMacHdr = SWAP16(*(USHORT *)pMacHdr);
// swab 16 bit fields - Listen Interval field
pMacHdr += 2;
*(USHORT *)pMacHdr = SWAP16(*(USHORT *)pMacHdr);
break;
case SUBTYPE_ASSOC_RSP:
case SUBTYPE_REASSOC_RSP:
// swab 16 bit fields - CapabilityInfo field
pMacHdr += sizeof(HEADER_802_11);
*(USHORT *)pMacHdr = SWAP16(*(USHORT *)pMacHdr);
// swab 16 bit fields - Status Code field
pMacHdr += 2;
*(USHORT *)pMacHdr = SWAP16(*(USHORT *)pMacHdr);
// swab 16 bit fields - AID field
pMacHdr += 2;
*(USHORT *)pMacHdr = SWAP16(*(USHORT *)pMacHdr);
break;
case SUBTYPE_AUTH:
// If from APHandleRxDoneInterrupt routine, it is still a encrypt format.
// The convertion is delayed to RTMPHandleDecryptionDoneInterrupt.
if(!FromRxDoneInt && pFrame->FC.Wep == 1)
break;
else
{
// swab 16 bit fields - Auth Alg No. field
pMacHdr += sizeof(HEADER_802_11);
*(USHORT *)pMacHdr = SWAP16(*(USHORT *)pMacHdr);
// swab 16 bit fields - Auth Seq No. field
pMacHdr += 2;
*(USHORT *)pMacHdr = SWAP16(*(USHORT *)pMacHdr);
// swab 16 bit fields - Status Code field
pMacHdr += 2;
*(USHORT *)pMacHdr = SWAP16(*(USHORT *)pMacHdr);
}
break;
case SUBTYPE_BEACON:
case SUBTYPE_PROBE_RSP:
// swab 16 bit fields - BeaconInterval field
pMacHdr += (sizeof(HEADER_802_11) + TIMESTAMP_LEN);
*(USHORT *)pMacHdr = SWAP16(*(USHORT *)pMacHdr);
// swab 16 bit fields - CapabilityInfo field
pMacHdr += sizeof(USHORT);
*(USHORT *)pMacHdr = SWAP16(*(USHORT *)pMacHdr);
break;
case SUBTYPE_DEAUTH:
case SUBTYPE_DISASSOC:
// swab 16 bit fields - Reason code field
pMacHdr += sizeof(HEADER_802_11);
*(USHORT *)pMacHdr = SWAP16(*(USHORT *)pMacHdr);
break;
}
}
else if( pFrame->FC.Type == BTYPE_DATA )
{
}
else if(pFrame->FC.Type == BTYPE_CNTL)
{
switch(pFrame->FC.SubType)
{
case SUBTYPE_BLOCK_ACK_REQ:
{
PFRAME_BA_REQ pBAReq = (PFRAME_BA_REQ)pFrame;
*(USHORT *)(&pBAReq->BARControl) = SWAP16(*(USHORT *)(&pBAReq->BARControl));
pBAReq->BAStartingSeq.word = SWAP16(pBAReq->BAStartingSeq.word);
}
break;
case SUBTYPE_BLOCK_ACK:
// For Block Ack packet, the HT_CONTROL field is in the same offset with Addr3
*(UINT32 *)(&pFrame->Addr3[0]) = SWAP32(*(UINT32 *)(&pFrame->Addr3[0]));
break;
case SUBTYPE_ACK:
//For ACK packet, the HT_CONTROL field is in the same offset with Addr2
*(UINT32 *)(&pFrame->Addr2[0])= SWAP32(*(UINT32 *)(&pFrame->Addr2[0]));
break;
}
}
else
{
DBGPRINT(RT_DEBUG_ERROR,("Invalid Frame Type!!!\n"));
}
// swab 16 bit fields - Frame Control
if(Dir == DIR_WRITE)
{
*(USHORT *)pData = SWAP16(*(USHORT *)pData);
}
}
#endif // RT_BIG_ENDIAN //
static inline VOID ConvertMulticastIP2MAC(
IN PUCHAR pIpAddr,
IN PUCHAR *ppMacAddr,

30
drivers/staging/rt2860/rtmp_def.h
View File

@ -1249,17 +1249,6 @@
#define OPMODE_AP 1
//#define OPMODE_L3_BRG 2 // as AP and STA at the same time
#ifdef RT_BIG_ENDIAN
#define DIR_READ 0
#define DIR_WRITE 1
#define TYPE_TXD 0
#define TYPE_RXD 1
#define TYPE_TXINFO 0
#define TYPE_RXINFO 1
#define TYPE_TXWI 0
#define TYPE_RXWI 1
#endif
// ========================= AP rtmp_def.h ===========================
// value domain for pAd->EventTab.Log[].Event
#define EVENT_RESET_ACCESS_POINT 0 // Log = "hh:mm:ss Restart Access Point"
@ -1440,23 +1429,6 @@
(UINT64)(((UINT64)(x) & (UINT64) 0x00ff000000000000ULL) >> 40) | \
(UINT64)(((UINT64)(x) & (UINT64) 0xff00000000000000ULL) >> 56) ))
#ifdef RT_BIG_ENDIAN
#define cpu2le64(x) SWAP64((x))
#define le2cpu64(x) SWAP64((x))
#define cpu2le32(x) SWAP32((x))
#define le2cpu32(x) SWAP32((x))
#define cpu2le16(x) SWAP16((x))
#define le2cpu16(x) SWAP16((x))
#define cpu2be64(x) ((UINT64)(x))
#define be2cpu64(x) ((UINT64)(x))
#define cpu2be32(x) ((UINT32)(x))
#define be2cpu32(x) ((UINT32)(x))
#define cpu2be16(x) ((UINT16)(x))
#define be2cpu16(x) ((UINT16)(x))
#else // Little_Endian
#define cpu2le64(x) ((UINT64)(x))
#define le2cpu64(x) ((UINT64)(x))
#define cpu2le32(x) ((UINT32)(x))
@ -1470,8 +1442,6 @@
#define cpu2be16(x) SWAP16((x))
#define be2cpu16(x) SWAP16((x))
#endif // RT_BIG_ENDIAN
#endif // __RTMP_DEF_H__

30
drivers/staging/rt2860/spectrum.h
View File

@ -46,16 +46,6 @@ typedef struct PACKED _CH_SW_ANN_INFO
typedef union PACKED _MEASURE_REQ_MODE
{
#ifdef RT_BIG_ENDIAN
struct PACKED
{
UINT8 Rev1:4;
UINT8 Report:1;
UINT8 Request:1;
UINT8 Enable:1;
UINT8 Rev0:1;
} field;
#else
struct PACKED
{
UINT8 Rev0:1;
@ -64,7 +54,6 @@ typedef union PACKED _MEASURE_REQ_MODE
UINT8 Report:1;
UINT8 Rev1:4;
} field;
#endif // RT_BIG_ENDIAN //
UINT8 word;
} MEASURE_REQ_MODE, *PMEASURE_REQ_MODE;
@ -85,17 +74,6 @@ typedef struct PACKED _MEASURE_REQ_INFO
typedef union PACKED _MEASURE_BASIC_REPORT_MAP
{
#ifdef RT_BIG_ENDIAN
struct PACKED
{
UINT8 Rev:3;
UINT8 Unmeasure:1;
UINT8 Radar:1;
UINT8 UnidentifiedSignal:1;
UINT8 OfdmPreamble:1;
UINT8 BSS:1;
} field;
#else
struct PACKED
{
UINT8 BSS:1;
@ -105,7 +83,6 @@ typedef union PACKED _MEASURE_BASIC_REPORT_MAP
UINT8 Unmeasure:1;
UINT8 Rev:3;
} field;
#endif // RT_BIG_ENDIAN //
UINT8 word;
} MEASURE_BASIC_REPORT_MAP, *PMEASURE_BASIC_REPORT_MAP;
@ -137,17 +114,10 @@ typedef union PACKED _MEASURE_REPORT_MODE
{
struct PACKED
{
#ifdef RT_BIG_ENDIAN
UINT8 Rev:5;
UINT8 Refused:1;
UINT8 Incapable:1;
UINT8 Late:1;
#else
UINT8 Late:1;
UINT8 Incapable:1;
UINT8 Refused:1;
UINT8 Rev:5;
#endif // RT_BIG_ENDIAN //
} field;
UINT8 word;
} MEASURE_REPORT_MODE, *PMEASURE_REPORT_MODE;

17
drivers/staging/rt2860/sta/assoc.c
View File

@ -360,28 +360,11 @@ VOID MlmeAssocReqAction(
}
else
{
#ifdef RT_BIG_ENDIAN
HT_CAPABILITY_IE HtCapabilityTmp;
#endif
#ifndef RT_BIG_ENDIAN
MakeOutgoingFrame(pOutBuffer + FrameLen, &TmpLen,
1, &HtCapIe,
1, &pAd->MlmeAux.HtCapabilityLen,
pAd->MlmeAux.HtCapabilityLen, &pAd->MlmeAux.HtCapability,
END_OF_ARGS);
#else
NdisZeroMemory(&HtCapabilityTmp, sizeof(HT_CAPABILITY_IE));
NdisMoveMemory(&HtCapabilityTmp, &pAd->MlmeAux.HtCapability, pAd->MlmeAux.HtCapabilityLen);
*(USHORT *)(&HtCapabilityTmp.HtCapInfo) = SWAP16(*(USHORT *)(&HtCapabilityTmp.HtCapInfo));
*(USHORT *)(&HtCapabilityTmp.ExtHtCapInfo) = SWAP16(*(USHORT *)(&HtCapabilityTmp.ExtHtCapInfo));
MakeOutgoingFrame(pOutBuffer + FrameLen, &TmpLen,
1, &HtCapIe,
1, &pAd->MlmeAux.HtCapabilityLen,
pAd->MlmeAux.HtCapabilityLen,&HtCapabilityTmp,
END_OF_ARGS);
#endif
}
FrameLen += TmpLen;
}

30
drivers/staging/rt2860/sta/connect.c
View File

@ -2389,16 +2389,10 @@ ULONG MakeIbssBeacon(
ULONG TmpLen;
UCHAR HtLen, HtLen1;
#ifdef RT_BIG_ENDIAN
HT_CAPABILITY_IE HtCapabilityTmp;
ADD_HT_INFO_IE addHTInfoTmp;
USHORT b2lTmp, b2lTmp2;
#endif
// add HT Capability IE
HtLen = sizeof(pAd->CommonCfg.HtCapability);
HtLen1 = sizeof(pAd->CommonCfg.AddHTInfo);
#ifndef RT_BIG_ENDIAN
MakeOutgoingFrame(pBeaconFrame+FrameLen, &TmpLen,
1, &HtCapIe,
1, &HtLen,
@ -2407,24 +2401,7 @@ ULONG MakeIbssBeacon(
1, &HtLen1,
HtLen1, &pAd->CommonCfg.AddHTInfo,
END_OF_ARGS);
#else
NdisMoveMemory(&HtCapabilityTmp, &pAd->CommonCfg.HtCapability, HtLen);
*(USHORT *)(&HtCapabilityTmp.HtCapInfo) = SWAP16(*(USHORT *)(&HtCapabilityTmp.HtCapInfo));
*(USHORT *)(&HtCapabilityTmp.ExtHtCapInfo) = SWAP16(*(USHORT *)(&HtCapabilityTmp.ExtHtCapInfo));
NdisMoveMemory(&addHTInfoTmp, &pAd->CommonCfg.AddHTInfo, HtLen1);
*(USHORT *)(&addHTInfoTmp.AddHtInfo2) = SWAP16(*(USHORT *)(&addHTInfoTmp.AddHtInfo2));
*(USHORT *)(&addHTInfoTmp.AddHtInfo3) = SWAP16(*(USHORT *)(&addHTInfoTmp.AddHtInfo3));
MakeOutgoingFrame(pBeaconFrame+FrameLen, &TmpLen,
1, &HtCapIe,
1, &HtLen,
HtLen, &HtCapabilityTmp,
1, &AddHtInfoIe,
1, &HtLen1,
HtLen1, &addHTInfoTmp,
END_OF_ARGS);
#endif
FrameLen += TmpLen;
}
#endif // DOT11_N_SUPPORT //
@ -2444,11 +2421,6 @@ ULONG MakeIbssBeacon(
PID_MGMT, PID_BEACON, RATE_1, IFS_HTTXOP, FALSE, &Transmit);
}
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, pBeaconFrame, DIR_WRITE, FALSE);
RTMPWIEndianChange((PUCHAR)pTxWI, TYPE_TXWI);
#endif
DBGPRINT(RT_DEBUG_TRACE, ("MakeIbssBeacon (len=%ld), SupRateLen=%d, ExtRateLen=%d, Channel=%d, PhyMode=%d\n",
FrameLen, SupRateLen, ExtRateLen, pAd->CommonCfg.Channel, pAd->CommonCfg.PhyMode));
return FrameLen;

5
drivers/staging/rt2860/sta/rtmp_data.c
View File

@ -687,11 +687,6 @@ BOOLEAN STARxDoneInterruptHandle(
pRxWI = (PRXWI_STRUC) pData;
pHeader = (PHEADER_802_11) (pData+RXWI_SIZE) ;
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (PUCHAR)pHeader, DIR_READ, TRUE);
RTMPWIEndianChange((PUCHAR)pRxWI, TYPE_RXWI);
#endif
// build RxCell
RxCell.pRxWI = pRxWI;
RxCell.pHeader = pHeader;

29
drivers/staging/rt2860/wpa.h
View File

@ -150,19 +150,6 @@
// EAPOL Key Information definition within Key descriptor format
typedef struct PACKED _KEY_INFO
{
#ifdef RT_BIG_ENDIAN
UCHAR KeyAck:1;
UCHAR Install:1;
UCHAR KeyIndex:2;
UCHAR KeyType:1;
UCHAR KeyDescVer:3;
UCHAR Rsvd:3;
UCHAR EKD_DL:1; // EKD for AP; DL for STA
UCHAR Request:1;
UCHAR Error:1;
UCHAR Secure:1;
UCHAR KeyMic:1;
#else
UCHAR KeyMic:1;
UCHAR Secure:1;
UCHAR Error:1;
@ -174,7 +161,6 @@ typedef struct PACKED _KEY_INFO
UCHAR KeyIndex:2;
UCHAR Install:1;
UCHAR KeyAck:1;
#endif
} KEY_INFO, *PKEY_INFO;
// EAPOL Key descriptor format
@ -204,17 +190,10 @@ typedef struct PACKED _EAPOL_PACKET
//802.11i D10 page 83
typedef struct PACKED _GTK_ENCAP
{
#ifndef RT_BIG_ENDIAN
UCHAR Kid:2;
UCHAR tx:1;
UCHAR rsv:5;
UCHAR rsv1;
#else
UCHAR rsv:5;
UCHAR tx:1;
UCHAR Kid:2;
UCHAR rsv1;
#endif
UCHAR GTK[TKIP_GTK_LENGTH];
} GTK_ENCAP, *PGTK_ENCAP;
@ -258,19 +237,11 @@ typedef struct PACKED _RSNIE_AUTH {
typedef union PACKED _RSN_CAPABILITIES {
struct PACKED {
#ifdef RT_BIG_ENDIAN
USHORT Rsvd:10;
USHORT GTKSA_R_Counter:2;
USHORT PTKSA_R_Counter:2;
USHORT No_Pairwise:1;
USHORT PreAuth:1;
#else
USHORT PreAuth:1;
USHORT No_Pairwise:1;
USHORT PTKSA_R_Counter:2;
USHORT GTKSA_R_Counter:2;
USHORT Rsvd:10;
#endif
} field;
USHORT word;
} RSN_CAPABILITIES, *PRSN_CAPABILITIES;