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iio: adc: max11100: Fix alignment for DMA safety 

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Update the comment to include 'may'.

Fixes: a8e7e88df9 ("iio: adc: Add Maxim MAX11100 driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Jacopo Mondi <jacopo@jmondi.org>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-25-jic23@kernel.org
This commit is contained in:
Jonathan Cameron 2022-05-08 18:56:04 +01:00
parent e754fb7e7a
commit 51f30d6314
1 changed files with 2 additions and 2 deletions
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4
drivers/iio/adc/max11100.c
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@ -33,10 +33,10 @@ struct max11100_state {
struct spi_device *spi;
/*
* DMA (thus cache coherency maintenance) requires the
* DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines.
*/
u8 buffer[3] ____cacheline_aligned;
u8 buffer[3] __aligned(IIO_DMA_MINALIGN);
};
static const struct iio_chan_spec max11100_channels[] = {