Renesas ARM Based SoC DT Updates for v4.21
* RZ/N1D (r9a06g032) SoC: - Correct GIC DT node name - Enable pin controller * RZ/G1C (r8a77470) iWave g23S single board computer - Add QSPI flash support - Add pinctl support for EtherAVB - Enable CMT0 (Renesas R-Car Compare Match Timer) - Enable RWDT (Renesas Watchdog Timer) - Enable uSD and eMMC support * RZ/G1C (r8a77470) SoC: - Describe USB-DMAC and I2C devices in DT * R-Mobile A1 (r8a7740), Emma Mobile EV2 (emev2) and SH-Mobile AG5 (sh72a0) SoCs: - Include SoC name in DTSI * R-Car H2 (r8a7790) based lager, and R-Car M2-W (r8a7791) based koelsch and porter boards: - Disable unconnected LVDS encoders -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE4nzZofWswv9L/nKF189kaWo3T74FAlv+kMsACgkQ189kaWo3 T75B2Q//chiLcnE7zNwwoMnNlDnlmUaEmi8xEENVRcEXr6plHniDASMK52aZuQvJ zBAjJ/WaWQbxOjS+fKMO/nUH2x/8pMpd8GqClTYd82NTC0jIP90asTCIoacRoV8u iCA0wxG0bn1ytzFn+obor40750TVvLBFY+wdNHVVf/l+l/SasispuCfOVqYII57G SENuxT3qRU/4twDCjnBxZP8Qo8ozZU9BH5of3NKM0mxnRGh2sCIpzNWB94pBR+eA MCSgFFpMVsb3GUqsfMEtOKoyyiINTROnbD4WYG8Uputewg07P8JAG6Te0wsrd0dd EhlQjmMtppyfoL7046avKefrfX/wrZfyG0IFUGpXGa/uIKUv+eH2IBXCD9ZeDUHt IALxjfhWppSzAyV6yS02Xw0gd3VRUpA8qB58g2pntsUBkU1UVjv0dJVGIAMgI5QY K/wfJ4K4IGUoxYNtnswBVvFI1Yil0mzxU1t8TPKtyTWxxsoEV10sTwYRf0uycGis vq8ZmDzgL7o+V3OFtSPW7HDYCyA+9MGVShuIFm/7qGMVsHJtEXe3wBjStu6Hb9iT ZgodY/bTWdxuetaR7lePRUUVzwUvdrg2N47e2DgFjw0Fx8r0wPy9S6B4Op3tTeEx uF+8RfKoVURg9CSlNU5c0bszJPkYa5q5BpeSNpc50s1q2ix0q+o= =jcXN -----END PGP SIGNATURE----- Merge tag 'renesas-arm-dt-for-v4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt Renesas ARM Based SoC DT Updates for v4.21 * RZ/N1D (r9a06g032) SoC: - Correct GIC DT node name - Enable pin controller * RZ/G1C (r8a77470) iWave g23S single board computer - Add QSPI flash support - Add pinctl support for EtherAVB - Enable CMT0 (Renesas R-Car Compare Match Timer) - Enable RWDT (Renesas Watchdog Timer) - Enable uSD and eMMC support * RZ/G1C (r8a77470) SoC: - Describe USB-DMAC and I2C devices in DT * R-Mobile A1 (r8a7740), Emma Mobile EV2 (emev2) and SH-Mobile AG5 (sh72a0) SoCs: - Include SoC name in DTSI * R-Car H2 (r8a7790) based lager, and R-Car M2-W (r8a7791) based koelsch and porter boards: - Disable unconnected LVDS encoders * tag 'renesas-arm-dt-for-v4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: dts: r9a06g032: Correct the GIC DT node name ARM: dts: iwg23s-sbc: Add QSPI flash support ARM: dts: r8a77470: Add QSPI support ARM: dts: iwg23s-sbc: Add pinctl support for EtherAVB ARM: dts: iwg23s-sbc: Enable cmt0 ARM: dts: r8a77470: Add CMT SoC specific support ARM: dts: r8a77470: Add USB-DMAC device nodes ARM: dts: iwg23s-sbc: Enable watchdog support ARM: dts: r8a77470: Add watchdog support to SoC dtsi ARM: dts: r8a7740, emev2, sh73a0: Include SoC name in DTSI ARM: dts: r8a779[01]: Disable unconnected LVDS encoders ARM: dts: iwg23s-sbc: Add uSD and eMMC support ARM: dts: r8a77470: Add SDHI1 support ARM: dts: r8a77470: Add SDHI0 support ARM: dts: r8a77470: Add I2C[0123] support ARM: dts: r9a06g032: Add pinctrl node Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
51ea46e828
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the EMEV2 SoC
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* Device Tree Source for the Emma Mobile EV2 SoC
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*
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* Copyright (C) 2012 Renesas Solutions Corp.
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*/
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the r8a7740 SoC
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* Device Tree Source for the R-Mobile A1 (R8A77400) SoC
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*
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* Copyright (C) 2012 Renesas Solutions Corp.
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*/
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@ -6,6 +6,7 @@
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "r8a77470.dtsi"
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/ {
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model = "iWave iW-RainboW-G23S single board computer based on RZ/G1C";
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@ -25,9 +26,43 @@
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device_type = "memory";
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reg = <0 0x40000000 0 0x20000000>;
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};
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reg_1p8v: reg-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_3p3v: reg-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vccq_sdhi2: regulator-vccq-sdhi2 {
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compatible = "regulator-gpio";
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regulator-name = "SDHI2 VccQ";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
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gpios-states = <1>;
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states = <3300000 1
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1800000 0>;
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};
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};
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&avb {
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pinctrl-0 = <&avb_pins>;
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pinctrl-names = "default";
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phy-handle = <&phy3>;
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phy-mode = "gmii";
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renesas,no-ether-link;
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@ -41,15 +76,73 @@
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};
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};
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&cmt0 {
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status = "okay";
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};
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&extal_clk {
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clock-frequency = <20000000>;
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};
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&pfc {
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avb_pins: avb {
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groups = "avb_mdio", "avb_gmii_tx_rx";
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function = "avb";
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};
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mmc_pins_uhs: mmc_uhs {
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groups = "mmc_data8", "mmc_ctrl";
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function = "mmc";
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power-source = <1800>;
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};
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qspi0_pins: qspi0 {
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groups = "qspi0_ctrl", "qspi0_data2";
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function = "qspi0";
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};
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scif1_pins: scif1 {
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groups = "scif1_data_b";
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function = "scif1";
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};
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sdhi2_pins: sd2 {
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groups = "sdhi2_data4", "sdhi2_ctrl";
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function = "sdhi2";
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power-source = <3300>;
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};
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sdhi2_pins_uhs: sd2_uhs {
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groups = "sdhi2_data4", "sdhi2_ctrl";
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function = "sdhi2";
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power-source = <1800>;
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};
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};
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&qspi0 {
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pinctrl-0 = <&qspi0_pins>;
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pinctrl-names = "default";
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status = "okay";
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/* WARNING - This device contains the bootloader. Handle with care. */
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flash: flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "issi,is25lp016d", "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <133000000>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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m25p,fast-read;
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spi-cpol;
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spi-cpha;
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};
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};
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&rwdt {
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timeout-sec = <60>;
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status = "okay";
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};
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&scif1 {
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@ -58,3 +151,29 @@
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status = "okay";
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};
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&sdhi1 {
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pinctrl-0 = <&mmc_pins_uhs>;
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pinctrl-names = "state_uhs";
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_1p8v>;
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bus-width = <8>;
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mmc-hs200-1_8v;
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non-removable;
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fixed-emmc-driver-type = <1>;
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status = "okay";
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};
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&sdhi2 {
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pinctrl-0 = <&sdhi2_pins>;
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pinctrl-1 = <&sdhi2_pins_uhs>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <&vccq_sdhi2>;
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bus-width = <4>;
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cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
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sd-uhs-sdr50;
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status = "okay";
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};
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@ -14,6 +14,14 @@
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -71,6 +79,16 @@
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#size-cells = <2>;
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ranges;
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rwdt: watchdog@e6020000 {
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compatible = "renesas,r8a77470-wdt",
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"renesas,rcar-gen2-wdt";
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reg = <0 0xe6020000 0 0x0c>;
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clocks = <&cpg CPG_MOD 402>;
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power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
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resets = <&cpg 402>;
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status = "disabled";
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};
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gpio0: gpio@e6050000 {
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compatible = "renesas,gpio-r8a77470",
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"renesas,rcar-gen2-gpio";
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@ -237,6 +255,62 @@
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reg = <0 0xe6300000 0 0x20000>;
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};
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i2c0: i2c@e6508000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a77470",
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"renesas,rcar-gen2-i2c";
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reg = <0 0xe6508000 0 0x40>;
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interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 931>;
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power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
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resets = <&cpg 931>;
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i2c-scl-internal-delay-ns = <6>;
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status = "disabled";
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};
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i2c1: i2c@e6518000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a77470",
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"renesas,rcar-gen2-i2c";
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reg = <0 0xe6518000 0 0x40>;
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interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 930>;
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power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
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resets = <&cpg 930>;
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i2c-scl-internal-delay-ns = <6>;
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status = "disabled";
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};
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i2c2: i2c@e6530000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a77470",
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"renesas,rcar-gen2-i2c";
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reg = <0 0xe6530000 0 0x40>;
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interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 929>;
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power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
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resets = <&cpg 929>;
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i2c-scl-internal-delay-ns = <6>;
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status = "disabled";
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};
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i2c3: i2c@e6540000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a77470",
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"renesas,rcar-gen2-i2c";
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reg = <0 0xe6540000 0 0x40>;
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interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 928>;
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power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
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resets = <&cpg 928>;
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i2c-scl-internal-delay-ns = <6>;
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status = "disabled";
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};
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i2c4: i2c@e6520000 {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -251,6 +325,62 @@
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status = "disabled";
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};
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usb_dmac00: dma-controller@e65a0000 {
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compatible = "renesas,r8a77470-usb-dmac",
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"renesas,usb-dmac";
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reg = <0 0xe65a0000 0 0x100>;
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interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "ch0", "ch1";
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clocks = <&cpg CPG_MOD 330>;
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power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
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resets = <&cpg 330>;
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#dma-cells = <1>;
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dma-channels = <2>;
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};
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usb_dmac10: dma-controller@e65b0000 {
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compatible = "renesas,r8a77470-usb-dmac",
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"renesas,usb-dmac";
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reg = <0 0xe65b0000 0 0x100>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "ch0", "ch1";
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clocks = <&cpg CPG_MOD 331>;
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power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
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resets = <&cpg 331>;
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#dma-cells = <1>;
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dma-channels = <2>;
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};
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usb_dmac01: dma-controller@e65a8000 {
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compatible = "renesas,r8a77470-usb-dmac",
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"renesas,usb-dmac";
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reg = <0 0xe65a8000 0 0x100>;
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interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "ch0", "ch1";
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clocks = <&cpg CPG_MOD 326>;
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power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
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resets = <&cpg 326>;
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#dma-cells = <1>;
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dma-channels = <2>;
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};
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usb_dmac11: dma-controller@e65b8000 {
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compatible = "renesas,r8a77470-usb-dmac",
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"renesas,usb-dmac";
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reg = <0 0xe65b8000 0 0x100>;
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interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "ch0", "ch1";
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clocks = <&cpg CPG_MOD 327>;
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power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
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resets = <&cpg 327>;
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#dma-cells = <1>;
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dma-channels = <2>;
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};
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|
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dmac0: dma-controller@e6700000 {
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compatible = "renesas,dmac-r8a77470",
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"renesas,rcar-dmac";
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@ -330,6 +460,38 @@
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status = "disabled";
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||||
};
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||||
|
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qspi0: spi@e6b10000 {
|
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compatible = "renesas,qspi-r8a77470", "renesas,qspi";
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reg = <0 0xe6b10000 0 0x2c>;
|
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interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 918>;
|
||||
dmas = <&dmac0 0x17>, <&dmac0 0x18>,
|
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<&dmac1 0x17>, <&dmac1 0x18>;
|
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dma-names = "tx", "rx", "tx", "rx";
|
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power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
resets = <&cpg 918>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qspi1: spi@ee200000 {
|
||||
compatible = "renesas,qspi-r8a77470", "renesas,qspi";
|
||||
reg = <0 0xee200000 0 0x2c>;
|
||||
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
|
||||
<&dmac1 0xd1>, <&dmac1 0xd2>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
resets = <&cpg 917>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif0: serial@e6e60000 {
|
||||
compatible = "renesas,scif-r8a77470",
|
||||
"renesas,rcar-gen2-scif", "renesas,scif";
|
||||
|
|
@ -426,6 +588,32 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi0: sd@ee100000 {
|
||||
compatible = "renesas,sdhi-r8a77470",
|
||||
"renesas,rcar-gen2-sdhi";
|
||||
reg = <0 0xee100000 0 0x328>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
|
||||
<&dmac1 0xcd>, <&dmac1 0xce>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
max-frequency = <156000000>;
|
||||
power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 314>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi1: sd@ee300000 {
|
||||
compatible = "renesas,sdhi-mmc-r8a77470";
|
||||
reg = <0 0xee300000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 313>;
|
||||
max-frequency = <156000000>;
|
||||
power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 313>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi2: sd@ee160000 {
|
||||
compatible = "renesas,sdhi-r8a77470",
|
||||
"renesas,rcar-gen2-sdhi";
|
||||
|
|
@ -435,7 +623,7 @@
|
|||
dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
|
||||
<&dmac1 0xd3>, <&dmac1 0xd4>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
max-frequency = <97500000>;
|
||||
max-frequency = <78000000>;
|
||||
power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 312>;
|
||||
status = "disabled";
|
||||
|
|
@ -459,6 +647,38 @@
|
|||
compatible = "renesas,prr";
|
||||
reg = <0 0xff000044 0 4>;
|
||||
};
|
||||
|
||||
cmt0: timer@ffca0000 {
|
||||
compatible = "renesas,r8a77470-cmt0",
|
||||
"renesas,rcar-gen2-cmt0";
|
||||
reg = <0 0xffca0000 0 0x1004>;
|
||||
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 124>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 124>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cmt1: timer@e6130000 {
|
||||
compatible = "renesas,r8a77470-cmt1",
|
||||
"renesas,rcar-gen2-cmt1";
|
||||
reg = <0 0xe6130000 0 0x1004>;
|
||||
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 329>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 329>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
|
|
|
|||
|
|
@ -489,8 +489,6 @@
|
|||
};
|
||||
|
||||
&lvds1 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
lvds_connector: endpoint {
|
||||
|
|
|
|||
|
|
@ -479,8 +479,6 @@
|
|||
};
|
||||
|
||||
&lvds0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
lvds_connector: endpoint {
|
||||
|
|
|
|||
|
|
@ -482,8 +482,6 @@
|
|||
};
|
||||
|
||||
&lvds0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
lvds_connector: endpoint {
|
||||
|
|
|
|||
|
|
@ -165,7 +165,15 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: gic@44101000 {
|
||||
pinctrl: pin-controller@40067000 {
|
||||
compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
|
||||
reg = <0x40067000 0x1000>, <0x51000000 0x480>;
|
||||
clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
|
||||
clock-names = "bus";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@44101000 {
|
||||
compatible = "arm,cortex-a7-gic", "arm,gic-400";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the SH73A0 SoC
|
||||
* Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC
|
||||
*
|
||||
* Copyright (C) 2012 Renesas Solutions Corp.
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue