watchdog: at91sam9_wdt: better watchdog support
The at91sam9 watchdog timer can only be configured once, and the current implementation tries to configure it in a static way: - 2 seconds timeout - wdt restart every 500ms If the timer has already been configured with different values, it returns an error and do not create any watchdog device. This is not critical if the watchdog is disabled, but if it has been enabled with different timeout values it will lead to a SoC reset. This patch series tries to address this issue by adapting the heartbeat value according the WDT timer config: - it first tries to configure the timer as requested. - if it fails it fallbacks to the current config, adapting its heartbeat timer to the needs This patch series also move to a dynamically allocated at91wdt device instead of the static instance. It adds a new at91 wdt type: software. This new type make use of the at91 wdt interrupt to trigger a software reboot. Finally it adds several properties to the device tree bindings. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
This commit is contained in:
Boris BREZILLON
Wim Van Sebroeck
parent
e30722e497
commit
5161b31dc3
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@ -19,11 +19,13 @@
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/platform_device.h>
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#include <linux/reboot.h>
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#include <linux/types.h>
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#include <linux/watchdog.h>
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#include <linux/jiffies.h>
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@ -31,22 +33,33 @@
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#include <linux/bitops.h>
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#include <linux/uaccess.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include "at91sam9_wdt.h"
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#define DRV_NAME "AT91SAM9 Watchdog"
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#define wdt_read(field) \
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__raw_readl(at91wdt_private.base + field)
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#define wdt_write(field, val) \
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__raw_writel((val), at91wdt_private.base + field)
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#define wdt_read(wdt, field) \
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__raw_readl((wdt)->base + (field))
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#define wdt_write(wtd, field, val) \
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__raw_writel((val), (wdt)->base + (field))
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/* AT91SAM9 watchdog runs a 12bit counter @ 256Hz,
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* use this to convert a watchdog
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* value from/to milliseconds.
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*/
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#define ms_to_ticks(t) (((t << 8) / 1000) - 1)
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#define ticks_to_ms(t) (((t + 1) * 1000) >> 8)
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#define ticks_to_hz_rounddown(t) ((((t) + 1) * HZ) >> 8)
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#define ticks_to_hz_roundup(t) (((((t) + 1) * HZ) + 255) >> 8)
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#define ticks_to_secs(t) (((t) + 1) >> 8)
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#define secs_to_ticks(s) (((s) << 8) - 1)
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#define WDT_MR_RESET 0x3FFF2FFF
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/* Watchdog max counter value in ticks */
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#define WDT_COUNTER_MAX_TICKS 0xFFF
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/* Watchdog max delta/value in secs */
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#define WDT_COUNTER_MAX_SECS ticks_to_secs(WDT_COUNTER_MAX_TICKS)
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/* Hardware timeout in seconds */
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#define WDT_HW_TIMEOUT 2
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@ -66,23 +79,40 @@ module_param(nowayout, bool, 0);
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
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"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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static struct watchdog_device at91_wdt_dev;
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static void at91_ping(unsigned long data);
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static struct {
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#define to_wdt(wdd) container_of(wdd, struct at91wdt, wdd)
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struct at91wdt {
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struct watchdog_device wdd;
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void __iomem *base;
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unsigned long next_heartbeat; /* the next_heartbeat for the timer */
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struct timer_list timer; /* The timer that pings the watchdog */
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} at91wdt_private;
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u32 mr;
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u32 mr_mask;
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unsigned long heartbeat; /* WDT heartbeat in jiffies */
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bool nowayout;
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unsigned int irq;
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};
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/* ......................................................................... */
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static irqreturn_t wdt_interrupt(int irq, void *dev_id)
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{
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struct at91wdt *wdt = (struct at91wdt *)dev_id;
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if (wdt_read(wdt, AT91_WDT_SR)) {
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pr_crit("at91sam9 WDT software reset\n");
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emergency_restart();
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pr_crit("Reboot didn't ?????\n");
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}
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return IRQ_HANDLED;
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}
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/*
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* Reload the watchdog timer. (ie, pat the watchdog)
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*/
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static inline void at91_wdt_reset(void)
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static inline void at91_wdt_reset(struct at91wdt *wdt)
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{
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wdt_write(AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT);
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wdt_write(wdt, AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT);
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}
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/*
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@ -90,26 +120,21 @@ static inline void at91_wdt_reset(void)
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*/
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static void at91_ping(unsigned long data)
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{
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if (time_before(jiffies, at91wdt_private.next_heartbeat) ||
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(!watchdog_active(&at91_wdt_dev))) {
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at91_wdt_reset();
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mod_timer(&at91wdt_private.timer, jiffies + WDT_TIMEOUT);
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} else
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struct at91wdt *wdt = (struct at91wdt *)data;
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if (time_before(jiffies, wdt->next_heartbeat) ||
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!watchdog_active(&wdt->wdd)) {
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at91_wdt_reset(wdt);
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mod_timer(&wdt->timer, jiffies + wdt->heartbeat);
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} else {
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pr_crit("I will reset your machine !\n");
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}
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static int at91_wdt_ping(struct watchdog_device *wdd)
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{
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/* calculate when the next userspace timeout will be */
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at91wdt_private.next_heartbeat = jiffies + wdd->timeout * HZ;
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return 0;
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}
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}
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static int at91_wdt_start(struct watchdog_device *wdd)
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{
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/* calculate the next userspace timeout and modify the timer */
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at91_wdt_ping(wdd);
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mod_timer(&at91wdt_private.timer, jiffies + WDT_TIMEOUT);
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struct at91wdt *wdt = to_wdt(wdd);
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/* calculate when the next userspace timeout will be */
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wdt->next_heartbeat = jiffies + wdd->timeout * HZ;
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return 0;
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}
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@ -122,39 +147,89 @@ static int at91_wdt_stop(struct watchdog_device *wdd)
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static int at91_wdt_set_timeout(struct watchdog_device *wdd, unsigned int new_timeout)
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{
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wdd->timeout = new_timeout;
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return 0;
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return at91_wdt_start(wdd);
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}
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/*
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* Set the watchdog time interval in 1/256Hz (write-once)
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* Counter is 12 bit.
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*/
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static int at91_wdt_settimeout(unsigned int timeout)
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static int at91_wdt_init(struct platform_device *pdev, struct at91wdt *wdt)
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{
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unsigned int reg;
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unsigned int mr;
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u32 tmp;
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u32 delta;
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u32 value;
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int err;
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u32 mask = wdt->mr_mask;
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unsigned long min_heartbeat = 1;
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struct device *dev = &pdev->dev;
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/* Check if disabled */
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mr = wdt_read(AT91_WDT_MR);
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if (mr & AT91_WDT_WDDIS) {
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pr_err("sorry, watchdog is disabled\n");
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return -EIO;
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tmp = wdt_read(wdt, AT91_WDT_MR);
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if ((tmp & mask) != (wdt->mr & mask)) {
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if (tmp == WDT_MR_RESET) {
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wdt_write(wdt, AT91_WDT_MR, wdt->mr);
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tmp = wdt_read(wdt, AT91_WDT_MR);
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}
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}
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/*
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* All counting occurs at SLOW_CLOCK / 128 = 256 Hz
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*
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* Since WDV is a 12-bit counter, the maximum period is
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* 4096 / 256 = 16 seconds.
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*/
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reg = AT91_WDT_WDRSTEN /* causes watchdog reset */
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/* | AT91_WDT_WDRPROC causes processor reset only */
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| AT91_WDT_WDDBGHLT /* disabled in debug mode */
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| AT91_WDT_WDD /* restart at any time */
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| (timeout & AT91_WDT_WDV); /* timer value */
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wdt_write(AT91_WDT_MR, reg);
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if (tmp & AT91_WDT_WDDIS) {
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if (wdt->mr & AT91_WDT_WDDIS)
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return 0;
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dev_err(dev, "watchdog is disabled\n");
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return -EINVAL;
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}
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value = tmp & AT91_WDT_WDV;
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delta = (tmp & AT91_WDT_WDD) >> 16;
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if (delta < value)
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min_heartbeat = ticks_to_hz_roundup(value - delta);
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wdt->heartbeat = ticks_to_hz_rounddown(value);
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if (!wdt->heartbeat) {
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dev_err(dev,
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"heartbeat is too small for the system to handle it correctly\n");
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return -EINVAL;
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}
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if (wdt->heartbeat < min_heartbeat + 4) {
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wdt->heartbeat = min_heartbeat;
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dev_warn(dev,
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"min heartbeat and max heartbeat might be too close for the system to handle it correctly\n");
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if (wdt->heartbeat < 4)
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dev_warn(dev,
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"heartbeat might be too small for the system to handle it correctly\n");
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} else {
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wdt->heartbeat -= 4;
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}
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if ((tmp & AT91_WDT_WDFIEN) && wdt->irq) {
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err = request_irq(wdt->irq, wdt_interrupt,
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IRQF_SHARED | IRQF_IRQPOLL,
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pdev->name, wdt);
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if (err)
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return err;
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}
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if ((tmp & wdt->mr_mask) != (wdt->mr & wdt->mr_mask))
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dev_warn(dev,
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"watchdog already configured differently (mr = %x expecting %x)\n",
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tmp & wdt->mr_mask, wdt->mr & wdt->mr_mask);
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setup_timer(&wdt->timer, at91_ping, (unsigned long)wdt);
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mod_timer(&wdt->timer, jiffies + wdt->heartbeat);
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/* Try to set timeout from device tree first */
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if (watchdog_init_timeout(&wdt->wdd, 0, dev))
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watchdog_init_timeout(&wdt->wdd, heartbeat, dev);
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watchdog_set_nowayout(&wdt->wdd, wdt->nowayout);
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err = watchdog_register_device(&wdt->wdd);
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if (err)
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goto out_stop_timer;
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wdt->next_heartbeat = jiffies + wdt->wdd.timeout * HZ;
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return 0;
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out_stop_timer:
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del_timer(&wdt->timer);
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return err;
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}
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/* ......................................................................... */
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@ -169,61 +244,123 @@ static const struct watchdog_ops at91_wdt_ops = {
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.owner = THIS_MODULE,
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.start = at91_wdt_start,
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.stop = at91_wdt_stop,
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.ping = at91_wdt_ping,
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.set_timeout = at91_wdt_set_timeout,
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};
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static struct watchdog_device at91_wdt_dev = {
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.info = &at91_wdt_info,
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.ops = &at91_wdt_ops,
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.timeout = WDT_HEARTBEAT,
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.min_timeout = 1,
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.max_timeout = 0xFFFF,
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};
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#if defined(CONFIG_OF)
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static int of_at91wdt_init(struct device_node *np, struct at91wdt *wdt)
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{
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u32 min = 0;
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u32 max = WDT_COUNTER_MAX_SECS;
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const char *tmp;
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/* Get the interrupts property */
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wdt->irq = irq_of_parse_and_map(np, 0);
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if (!wdt->irq)
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dev_warn(wdt->wdd.parent, "failed to get IRQ from DT\n");
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if (!of_property_read_u32_index(np, "atmel,max-heartbeat-sec", 0,
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&max)) {
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if (!max || max > WDT_COUNTER_MAX_SECS)
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max = WDT_COUNTER_MAX_SECS;
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if (!of_property_read_u32_index(np, "atmel,min-heartbeat-sec",
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0, &min)) {
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if (min >= max)
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min = max - 1;
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}
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}
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min = secs_to_ticks(min);
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max = secs_to_ticks(max);
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wdt->mr_mask = 0x3FFFFFFF;
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wdt->mr = 0;
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if (!of_property_read_string(np, "atmel,watchdog-type", &tmp) &&
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!strcmp(tmp, "software")) {
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wdt->mr |= AT91_WDT_WDFIEN;
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wdt->mr_mask &= ~AT91_WDT_WDRPROC;
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} else {
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wdt->mr |= AT91_WDT_WDRSTEN;
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}
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if (!of_property_read_string(np, "atmel,reset-type", &tmp) &&
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!strcmp(tmp, "proc"))
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wdt->mr |= AT91_WDT_WDRPROC;
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if (of_property_read_bool(np, "atmel,disable")) {
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wdt->mr |= AT91_WDT_WDDIS;
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wdt->mr_mask &= AT91_WDT_WDDIS;
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}
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if (of_property_read_bool(np, "atmel,idle-halt"))
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wdt->mr |= AT91_WDT_WDIDLEHLT;
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if (of_property_read_bool(np, "atmel,dbg-halt"))
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wdt->mr |= AT91_WDT_WDDBGHLT;
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wdt->mr |= max | ((max - min) << 16);
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return 0;
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}
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#else
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static inline int of_at91wdt_init(struct device_node *np, struct at91wdt *wdt)
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{
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return 0;
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}
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#endif
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static int __init at91wdt_probe(struct platform_device *pdev)
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{
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struct resource *r;
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int res;
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int err;
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struct at91wdt *wdt;
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wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
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if (!wdt)
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return -ENOMEM;
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wdt->mr = (WDT_HW_TIMEOUT * 256) | AT91_WDT_WDRSTEN | AT91_WDT_WDD |
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AT91_WDT_WDDBGHLT | AT91_WDT_WDIDLEHLT;
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wdt->mr_mask = 0x3FFFFFFF;
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wdt->nowayout = nowayout;
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wdt->wdd.parent = &pdev->dev;
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wdt->wdd.info = &at91_wdt_info;
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wdt->wdd.ops = &at91_wdt_ops;
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wdt->wdd.timeout = WDT_HEARTBEAT;
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wdt->wdd.min_timeout = 1;
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wdt->wdd.max_timeout = 0xFFFF;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!r)
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return -ENODEV;
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at91wdt_private.base = ioremap(r->start, resource_size(r));
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if (!at91wdt_private.base) {
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dev_err(&pdev->dev, "failed to map registers, aborting.\n");
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return -ENOMEM;
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wdt->base = devm_ioremap_resource(&pdev->dev, r);
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if (IS_ERR(wdt->base))
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return PTR_ERR(wdt->base);
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if (pdev->dev.of_node) {
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err = of_at91wdt_init(pdev->dev.of_node, wdt);
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if (err)
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return err;
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}
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at91_wdt_dev.parent = &pdev->dev;
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watchdog_init_timeout(&at91_wdt_dev, heartbeat, &pdev->dev);
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watchdog_set_nowayout(&at91_wdt_dev, nowayout);
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err = at91_wdt_init(pdev, wdt);
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if (err)
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return err;
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/* Set watchdog */
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res = at91_wdt_settimeout(ms_to_ticks(WDT_HW_TIMEOUT * 1000));
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if (res)
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return res;
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res = watchdog_register_device(&at91_wdt_dev);
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if (res)
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return res;
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at91wdt_private.next_heartbeat = jiffies + at91_wdt_dev.timeout * HZ;
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setup_timer(&at91wdt_private.timer, at91_ping, 0);
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mod_timer(&at91wdt_private.timer, jiffies + WDT_TIMEOUT);
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platform_set_drvdata(pdev, wdt);
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pr_info("enabled (heartbeat=%d sec, nowayout=%d)\n",
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at91_wdt_dev.timeout, nowayout);
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wdt->wdd.timeout, wdt->nowayout);
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return 0;
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}
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static int __exit at91wdt_remove(struct platform_device *pdev)
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{
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watchdog_unregister_device(&at91_wdt_dev);
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struct at91wdt *wdt = platform_get_drvdata(pdev);
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watchdog_unregister_device(&wdt->wdd);
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pr_warn("I quit now, hardware will probably reboot!\n");
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del_timer(&at91wdt_private.timer);
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del_timer(&wdt->timer);
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return 0;
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}
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