ARM: perf: allocate CPU PMU dynamically at probe time
Supporting multiple, heterogeneous CPU PMUs requires us to allocate the arm_pmu structures dynamically as the devices are probed. This patch removes the static structure definitions for each CPU PMU type and instead passes pointers to the PMU-specific init functions. Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Sudeep KarkadaNagesha
Will Deacon
parent
e50c54189f
commit
513c99ce4e
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@ -23,6 +23,7 @@
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <asm/cputype.h>
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@ -195,13 +196,13 @@ static struct platform_device_id __devinitdata cpu_pmu_plat_device_ids[] = {
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/*
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* CPU PMU identification and probing.
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*/
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static struct arm_pmu *__devinit probe_current_pmu(void)
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static int __devinit probe_current_pmu(struct arm_pmu *pmu)
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{
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struct arm_pmu *pmu = NULL;
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int cpu = get_cpu();
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unsigned long cpuid = read_cpuid_id();
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unsigned long implementor = (cpuid & 0xFF000000) >> 24;
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unsigned long part_number = (cpuid & 0xFFF0);
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int ret = -ENODEV;
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pr_info("probing PMU on CPU %d\n", cpu);
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@ -211,25 +212,25 @@ static struct arm_pmu *__devinit probe_current_pmu(void)
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case 0xB360: /* ARM1136 */
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case 0xB560: /* ARM1156 */
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case 0xB760: /* ARM1176 */
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pmu = armv6pmu_init();
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ret = armv6pmu_init(pmu);
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break;
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case 0xB020: /* ARM11mpcore */
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pmu = armv6mpcore_pmu_init();
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ret = armv6mpcore_pmu_init(pmu);
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break;
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case 0xC080: /* Cortex-A8 */
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pmu = armv7_a8_pmu_init();
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ret = armv7_a8_pmu_init(pmu);
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break;
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case 0xC090: /* Cortex-A9 */
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pmu = armv7_a9_pmu_init();
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ret = armv7_a9_pmu_init(pmu);
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break;
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case 0xC050: /* Cortex-A5 */
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pmu = armv7_a5_pmu_init();
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ret = armv7_a5_pmu_init(pmu);
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break;
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case 0xC0F0: /* Cortex-A15 */
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pmu = armv7_a15_pmu_init();
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ret = armv7_a15_pmu_init(pmu);
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break;
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case 0xC070: /* Cortex-A7 */
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pmu = armv7_a7_pmu_init();
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ret = armv7_a7_pmu_init(pmu);
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break;
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}
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/* Intel CPUs [xscale]. */
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@ -237,39 +238,51 @@ static struct arm_pmu *__devinit probe_current_pmu(void)
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part_number = (cpuid >> 13) & 0x7;
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switch (part_number) {
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case 1:
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pmu = xscale1pmu_init();
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ret = xscale1pmu_init(pmu);
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break;
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case 2:
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pmu = xscale2pmu_init();
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ret = xscale2pmu_init(pmu);
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break;
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}
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}
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put_cpu();
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return pmu;
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return ret;
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}
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static int __devinit cpu_pmu_device_probe(struct platform_device *pdev)
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{
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const struct of_device_id *of_id;
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struct arm_pmu *(*init_fn)(void);
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int (*init_fn)(struct arm_pmu *);
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struct device_node *node = pdev->dev.of_node;
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struct arm_pmu *pmu;
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int ret = -ENODEV;
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if (cpu_pmu) {
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pr_info("attempt to register multiple PMU devices!");
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return -ENOSPC;
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}
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if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) {
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init_fn = of_id->data;
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cpu_pmu = init_fn();
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} else {
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cpu_pmu = probe_current_pmu();
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pmu = kzalloc(sizeof(struct arm_pmu), GFP_KERNEL);
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if (!pmu) {
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pr_info("failed to allocate PMU device!");
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return -ENOMEM;
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}
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if (!cpu_pmu)
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return -ENODEV;
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if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) {
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init_fn = of_id->data;
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ret = init_fn(pmu);
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} else {
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ret = probe_current_pmu(pmu);
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}
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if (ret) {
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pr_info("failed to register PMU devices!");
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kfree(pmu);
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return ret;
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}
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cpu_pmu = pmu;
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cpu_pmu->plat_device = pdev;
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cpu_pmu_init(cpu_pmu);
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register_cpu_notifier(&cpu_pmu_hotplug_notifier);
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@ -649,24 +649,22 @@ static int armv6_map_event(struct perf_event *event)
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&armv6_perf_cache_map, 0xFF);
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}
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static struct arm_pmu armv6pmu = {
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.name = "v6",
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.handle_irq = armv6pmu_handle_irq,
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.enable = armv6pmu_enable_event,
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.disable = armv6pmu_disable_event,
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.read_counter = armv6pmu_read_counter,
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.write_counter = armv6pmu_write_counter,
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.get_event_idx = armv6pmu_get_event_idx,
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.start = armv6pmu_start,
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.stop = armv6pmu_stop,
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.map_event = armv6_map_event,
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.num_events = 3,
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.max_period = (1LLU << 32) - 1,
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};
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static struct arm_pmu *__devinit armv6pmu_init(void)
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static int __devinit armv6pmu_init(struct arm_pmu *cpu_pmu)
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{
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return &armv6pmu;
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cpu_pmu->name = "v6";
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cpu_pmu->handle_irq = armv6pmu_handle_irq;
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cpu_pmu->enable = armv6pmu_enable_event;
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cpu_pmu->disable = armv6pmu_disable_event;
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cpu_pmu->read_counter = armv6pmu_read_counter;
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cpu_pmu->write_counter = armv6pmu_write_counter;
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cpu_pmu->get_event_idx = armv6pmu_get_event_idx;
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cpu_pmu->start = armv6pmu_start;
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cpu_pmu->stop = armv6pmu_stop;
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cpu_pmu->map_event = armv6_map_event;
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cpu_pmu->num_events = 3;
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cpu_pmu->max_period = (1LLU << 32) - 1;
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return 0;
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}
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/*
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@ -683,33 +681,31 @@ static int armv6mpcore_map_event(struct perf_event *event)
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&armv6mpcore_perf_cache_map, 0xFF);
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}
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static struct arm_pmu armv6mpcore_pmu = {
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.name = "v6mpcore",
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.handle_irq = armv6pmu_handle_irq,
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.enable = armv6pmu_enable_event,
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.disable = armv6mpcore_pmu_disable_event,
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.read_counter = armv6pmu_read_counter,
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.write_counter = armv6pmu_write_counter,
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.get_event_idx = armv6pmu_get_event_idx,
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.start = armv6pmu_start,
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.stop = armv6pmu_stop,
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.map_event = armv6mpcore_map_event,
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.num_events = 3,
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.max_period = (1LLU << 32) - 1,
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};
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static struct arm_pmu *__devinit armv6mpcore_pmu_init(void)
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static int __devinit armv6mpcore_pmu_init(struct arm_pmu *cpu_pmu)
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{
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return &armv6mpcore_pmu;
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cpu_pmu->name = "v6mpcore";
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cpu_pmu->handle_irq = armv6pmu_handle_irq;
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cpu_pmu->enable = armv6pmu_enable_event;
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cpu_pmu->disable = armv6mpcore_pmu_disable_event;
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cpu_pmu->read_counter = armv6pmu_read_counter;
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cpu_pmu->write_counter = armv6pmu_write_counter;
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cpu_pmu->get_event_idx = armv6pmu_get_event_idx;
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cpu_pmu->start = armv6pmu_start;
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cpu_pmu->stop = armv6pmu_stop;
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cpu_pmu->map_event = armv6mpcore_map_event;
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cpu_pmu->num_events = 3;
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cpu_pmu->max_period = (1LLU << 32) - 1;
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return 0;
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}
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#else
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static struct arm_pmu *__devinit armv6pmu_init(void)
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static int armv6pmu_init(struct arm_pmu *cpu_pmu)
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{
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return NULL;
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return -ENODEV;
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}
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static struct arm_pmu *__devinit armv6mpcore_pmu_init(void)
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static int armv6mpcore_pmu_init(struct arm_pmu *cpu_pmu)
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{
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return NULL;
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return -ENODEV;
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}
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#endif /* CONFIG_CPU_V6 || CONFIG_CPU_V6K */
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@ -18,8 +18,6 @@
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#ifdef CONFIG_CPU_V7
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static struct arm_pmu armv7pmu;
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/*
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* Common ARMv7 event types
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*
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@ -1014,7 +1012,7 @@ static void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
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* We only need to set the event for the cycle counter if we
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* have the ability to perform event filtering.
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*/
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if (armv7pmu.set_event_filter || idx != ARMV7_IDX_CYCLE_COUNTER)
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if (cpu_pmu->set_event_filter || idx != ARMV7_IDX_CYCLE_COUNTER)
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armv7_pmnc_write_evtsel(idx, hwc->config_base);
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/*
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@ -1232,17 +1230,18 @@ static int armv7_a7_map_event(struct perf_event *event)
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&armv7_a7_perf_cache_map, 0xFF);
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}
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static struct arm_pmu armv7pmu = {
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.handle_irq = armv7pmu_handle_irq,
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.enable = armv7pmu_enable_event,
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.disable = armv7pmu_disable_event,
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.read_counter = armv7pmu_read_counter,
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.write_counter = armv7pmu_write_counter,
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.get_event_idx = armv7pmu_get_event_idx,
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.start = armv7pmu_start,
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.stop = armv7pmu_stop,
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.reset = armv7pmu_reset,
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.max_period = (1LLU << 32) - 1,
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static void armv7pmu_init(struct arm_pmu *cpu_pmu)
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{
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cpu_pmu->handle_irq = armv7pmu_handle_irq;
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cpu_pmu->enable = armv7pmu_enable_event;
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cpu_pmu->disable = armv7pmu_disable_event;
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cpu_pmu->read_counter = armv7pmu_read_counter;
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cpu_pmu->write_counter = armv7pmu_write_counter;
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cpu_pmu->get_event_idx = armv7pmu_get_event_idx;
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cpu_pmu->start = armv7pmu_start;
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cpu_pmu->stop = armv7pmu_stop;
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cpu_pmu->reset = armv7pmu_reset;
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cpu_pmu->max_period = (1LLU << 32) - 1;
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};
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static u32 __devinit armv7_read_num_pmnc_events(void)
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@ -1256,70 +1255,75 @@ static u32 __devinit armv7_read_num_pmnc_events(void)
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return nb_cnt + 1;
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}
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static struct arm_pmu *__devinit armv7_a8_pmu_init(void)
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static int __devinit armv7_a8_pmu_init(struct arm_pmu *cpu_pmu)
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{
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armv7pmu.name = "ARMv7 Cortex-A8";
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armv7pmu.map_event = armv7_a8_map_event;
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armv7pmu.num_events = armv7_read_num_pmnc_events();
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return &armv7pmu;
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armv7pmu_init(cpu_pmu);
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cpu_pmu->name = "ARMv7 Cortex-A8";
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cpu_pmu->map_event = armv7_a8_map_event;
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cpu_pmu->num_events = armv7_read_num_pmnc_events();
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return 0;
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}
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static struct arm_pmu *__devinit armv7_a9_pmu_init(void)
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static int __devinit armv7_a9_pmu_init(struct arm_pmu *cpu_pmu)
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{
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armv7pmu.name = "ARMv7 Cortex-A9";
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armv7pmu.map_event = armv7_a9_map_event;
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armv7pmu.num_events = armv7_read_num_pmnc_events();
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return &armv7pmu;
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armv7pmu_init(cpu_pmu);
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cpu_pmu->name = "ARMv7 Cortex-A9";
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cpu_pmu->map_event = armv7_a9_map_event;
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cpu_pmu->num_events = armv7_read_num_pmnc_events();
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return 0;
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}
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static struct arm_pmu *__devinit armv7_a5_pmu_init(void)
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static int __devinit armv7_a5_pmu_init(struct arm_pmu *cpu_pmu)
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{
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armv7pmu.name = "ARMv7 Cortex-A5";
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armv7pmu.map_event = armv7_a5_map_event;
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armv7pmu.num_events = armv7_read_num_pmnc_events();
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return &armv7pmu;
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armv7pmu_init(cpu_pmu);
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cpu_pmu->name = "ARMv7 Cortex-A5";
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cpu_pmu->map_event = armv7_a5_map_event;
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cpu_pmu->num_events = armv7_read_num_pmnc_events();
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return 0;
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}
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static struct arm_pmu *__devinit armv7_a15_pmu_init(void)
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static int __devinit armv7_a15_pmu_init(struct arm_pmu *cpu_pmu)
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{
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armv7pmu.name = "ARMv7 Cortex-A15";
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armv7pmu.map_event = armv7_a15_map_event;
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armv7pmu.num_events = armv7_read_num_pmnc_events();
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armv7pmu.set_event_filter = armv7pmu_set_event_filter;
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return &armv7pmu;
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armv7pmu_init(cpu_pmu);
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cpu_pmu->name = "ARMv7 Cortex-A15";
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cpu_pmu->map_event = armv7_a15_map_event;
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cpu_pmu->num_events = armv7_read_num_pmnc_events();
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cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
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return 0;
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}
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static struct arm_pmu *__devinit armv7_a7_pmu_init(void)
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static int __devinit armv7_a7_pmu_init(struct arm_pmu *cpu_pmu)
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{
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armv7pmu.name = "ARMv7 Cortex-A7";
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armv7pmu.map_event = armv7_a7_map_event;
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armv7pmu.num_events = armv7_read_num_pmnc_events();
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armv7pmu.set_event_filter = armv7pmu_set_event_filter;
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return &armv7pmu;
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armv7pmu_init(cpu_pmu);
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cpu_pmu->name = "ARMv7 Cortex-A7";
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cpu_pmu->map_event = armv7_a7_map_event;
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cpu_pmu->num_events = armv7_read_num_pmnc_events();
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cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
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return 0;
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}
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#else
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static struct arm_pmu *__devinit armv7_a8_pmu_init(void)
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static inline int armv7_a8_pmu_init(struct arm_pmu *cpu_pmu)
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{
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return NULL;
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return -ENODEV;
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}
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static struct arm_pmu *__devinit armv7_a9_pmu_init(void)
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static inline int armv7_a9_pmu_init(struct arm_pmu *cpu_pmu)
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{
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return NULL;
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return -ENODEV;
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}
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static struct arm_pmu *__devinit armv7_a5_pmu_init(void)
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static inline int armv7_a5_pmu_init(struct arm_pmu *cpu_pmu)
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{
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return NULL;
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return -ENODEV;
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}
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static struct arm_pmu *__devinit armv7_a15_pmu_init(void)
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static inline int armv7_a15_pmu_init(struct arm_pmu *cpu_pmu)
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{
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return NULL;
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return -ENODEV;
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}
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static struct arm_pmu *__devinit armv7_a7_pmu_init(void)
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static inline int armv7_a7_pmu_init(struct arm_pmu *cpu_pmu)
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{
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return NULL;
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return -ENODEV;
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}
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#endif /* CONFIG_CPU_V7 */
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@ -434,24 +434,22 @@ static int xscale_map_event(struct perf_event *event)
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&xscale_perf_cache_map, 0xFF);
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}
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static struct arm_pmu xscale1pmu = {
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.name = "xscale1",
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.handle_irq = xscale1pmu_handle_irq,
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.enable = xscale1pmu_enable_event,
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.disable = xscale1pmu_disable_event,
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.read_counter = xscale1pmu_read_counter,
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.write_counter = xscale1pmu_write_counter,
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.get_event_idx = xscale1pmu_get_event_idx,
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.start = xscale1pmu_start,
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.stop = xscale1pmu_stop,
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.map_event = xscale_map_event,
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.num_events = 3,
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.max_period = (1LLU << 32) - 1,
|
||||
};
|
||||
|
||||
static struct arm_pmu *__devinit xscale1pmu_init(void)
|
||||
static int __devinit xscale1pmu_init(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
return &xscale1pmu;
|
||||
cpu_pmu->name = "xscale1";
|
||||
cpu_pmu->handle_irq = xscale1pmu_handle_irq;
|
||||
cpu_pmu->enable = xscale1pmu_enable_event;
|
||||
cpu_pmu->disable = xscale1pmu_disable_event;
|
||||
cpu_pmu->read_counter = xscale1pmu_read_counter;
|
||||
cpu_pmu->write_counter = xscale1pmu_write_counter;
|
||||
cpu_pmu->get_event_idx = xscale1pmu_get_event_idx;
|
||||
cpu_pmu->start = xscale1pmu_start;
|
||||
cpu_pmu->stop = xscale1pmu_stop;
|
||||
cpu_pmu->map_event = xscale_map_event;
|
||||
cpu_pmu->num_events = 3;
|
||||
cpu_pmu->max_period = (1LLU << 32) - 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define XSCALE2_OVERFLOWED_MASK 0x01f
|
||||
|
|
@ -801,33 +799,31 @@ xscale2pmu_write_counter(int counter, u32 val)
|
|||
}
|
||||
}
|
||||
|
||||
static struct arm_pmu xscale2pmu = {
|
||||
.name = "xscale2",
|
||||
.handle_irq = xscale2pmu_handle_irq,
|
||||
.enable = xscale2pmu_enable_event,
|
||||
.disable = xscale2pmu_disable_event,
|
||||
.read_counter = xscale2pmu_read_counter,
|
||||
.write_counter = xscale2pmu_write_counter,
|
||||
.get_event_idx = xscale2pmu_get_event_idx,
|
||||
.start = xscale2pmu_start,
|
||||
.stop = xscale2pmu_stop,
|
||||
.map_event = xscale_map_event,
|
||||
.num_events = 5,
|
||||
.max_period = (1LLU << 32) - 1,
|
||||
};
|
||||
|
||||
static struct arm_pmu *__devinit xscale2pmu_init(void)
|
||||
static int __devinit xscale2pmu_init(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
return &xscale2pmu;
|
||||
cpu_pmu->name = "xscale2";
|
||||
cpu_pmu->handle_irq = xscale2pmu_handle_irq;
|
||||
cpu_pmu->enable = xscale2pmu_enable_event;
|
||||
cpu_pmu->disable = xscale2pmu_disable_event;
|
||||
cpu_pmu->read_counter = xscale2pmu_read_counter;
|
||||
cpu_pmu->write_counter = xscale2pmu_write_counter;
|
||||
cpu_pmu->get_event_idx = xscale2pmu_get_event_idx;
|
||||
cpu_pmu->start = xscale2pmu_start;
|
||||
cpu_pmu->stop = xscale2pmu_stop;
|
||||
cpu_pmu->map_event = xscale_map_event;
|
||||
cpu_pmu->num_events = 5;
|
||||
cpu_pmu->max_period = (1LLU << 32) - 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
static struct arm_pmu *__devinit xscale1pmu_init(void)
|
||||
static inline int xscale1pmu_init(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
return NULL;
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static struct arm_pmu *__devinit xscale2pmu_init(void)
|
||||
static inline int xscale2pmu_init(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
return NULL;
|
||||
return -ENODEV;
|
||||
}
|
||||
#endif /* CONFIG_CPU_XSCALE */
|
||||
|
|
|
|||
Loading…
Reference in New Issue