pinctrl: sh-pfc: r8a7794: Rename some I2C signals
The R8A7794 PFC driver was apparently based on the preliminary revisions of the user's manual which called I2C5 device IIC0 and IIC0 device IIC1. Luckily, these signals haven't been used for any functions/groups so far, so the renaming should be painless.. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Sergei Shtylyov
Geert Uytterhoeven
parent
8df6270149
commit
5128238dd7
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@ -111,7 +111,7 @@ enum {
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FN_PWM5_C, FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
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FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D, FN_D13,
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FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B, FN_D14, FN_SCIFA1_RXD,
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FN_IIC0_SCL_B, FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B, FN_A0,
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FN_I2C5_SCL_B, FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B, FN_A0,
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FN_SCIFB1_SCK, FN_PWM3_B, FN_A1, FN_SCIFB1_TXD, FN_A3, FN_SCIFB0_SCK,
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FN_A4, FN_SCIFB0_TXD, FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
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FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
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@ -119,7 +119,7 @@ enum {
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/* IPSR2 */
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FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, FN_A8, FN_MSIOF1_RXD,
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FN_SCIFA0_RXD_B, FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, FN_A10,
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FN_MSIOF1_SCK, FN_IIC1_SCL_B, FN_A11, FN_MSIOF1_SYNC, FN_IIC1_SDA_B,
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FN_MSIOF1_SCK, FN_IIC0_SCL_B, FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B,
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FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, FN_A13, FN_MSIOF1_SS2,
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FN_SCIFA5_TXD_B, FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
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FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, FN_A16,
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@ -183,11 +183,11 @@ enum {
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FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, FN_VI0_HSYNC_N,
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FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, FN_VI0_VSYNC_N,
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FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN,
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FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, FN_AVB_TX_CLK,
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FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, FN_AVB_TX_CLK,
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FN_ADIDATA, FN_AD_DI,
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/* IPSR7 */
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FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, FN_AVB_TXD0,
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FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, FN_AVB_TXD0,
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FN_ADICS_SAMP, FN_AD_DO, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B,
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FN_CAN0_RX_B, FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, FN_ETH_RXD0, FN_VI0_G3,
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FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N,
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@ -195,8 +195,8 @@ enum {
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FN_ADICHS1, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
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FN_AVB_TXD4, FN_ADICHS2, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C,
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FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C,
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FN_IIC1_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0,
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FN_SCIF2_TXD_C, FN_IIC1_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B,
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FN_IIC0_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0,
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FN_SCIF2_TXD_C, FN_IIC0_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B,
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FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B,
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FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK,
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FN_SSI_WS6_B, FN_DREQ0_N, FN_SCIFB1_RXD,
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@ -235,11 +235,11 @@ enum {
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FN_DU1_DG5, FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34,
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/* IPSR10 */
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FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, FN_CAN_DEBUGOUT0,
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FN_CC50_STATE35, FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
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FN_CAN_DEBUGOUT1, FN_CC50_STATE36, FN_SCIF2_RXD, FN_IIC1_SCL,
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FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, FN_CAN_DEBUGOUT0,
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FN_CC50_STATE35, FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
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FN_CAN_DEBUGOUT1, FN_CC50_STATE36, FN_SCIF2_RXD, FN_IIC0_SCL,
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FN_DU1_DB0, FN_SSI_SDATA2_B, FN_USB0_EXTLP, FN_CAN_DEBUGOUT2,
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FN_CC50_STATE37, FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
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FN_CC50_STATE37, FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
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FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, FN_SCIF2_SCK, FN_IRQ1,
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FN_DU1_DB2, FN_SSI_WS9_B, FN_USB0_IDIN, FN_CAN_DEBUGOUT4,
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FN_CC50_STATE39, FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
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@ -260,8 +260,8 @@ enum {
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FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
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FN_CAN_DEBUGOUT14, FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
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FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, FN_SSI_SCK78,
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FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, FN_SSI_WS78,
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FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7,
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FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP, FN_SSI_WS78,
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FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7,
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FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_PCMOE_N,
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FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
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FN_AD_DI_B, FN_PCMWE_N, FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D,
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@ -277,9 +277,9 @@ enum {
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FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX, FN_SSI_SDATA4, FN_MLB_DAT,
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FN_IERX_B, FN_IRD_SCK, FN_SSI_SDATA8, FN_SCIF1_SCK_B,
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FN_PWM1_B, FN_IRQ9, FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, FN_SSI_SCK1,
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FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D,
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FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D,
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FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, FN_SSI_WS1, FN_SCIF1_TXD_B,
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FN_IIC1_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH,
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FN_IIC0_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH,
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FN_ETH_RX_ER_B, FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_SDATA, FN_VI1_DATA1,
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FN_ATAWR0_N, FN_ETH_RXD0_B, FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2,
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FN_MDATA, FN_ATAG0_N, FN_ETH_RXD1_B,
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@ -314,12 +314,12 @@ enum {
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FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, FN_SEL_I2C02_4,
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FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
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FN_SEL_I2C03_4, FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2,
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FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_IIC00_0, FN_SEL_IIC00_1,
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FN_SEL_IIC00_2, FN_SEL_IIC00_3, FN_SEL_AVB_0, FN_SEL_AVB_1,
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FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_I2C05_0, FN_SEL_I2C05_1,
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FN_SEL_I2C05_2, FN_SEL_I2C05_3, FN_SEL_AVB_0, FN_SEL_AVB_1,
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/* MOD_SEL2 */
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FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC01_0,
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FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, FN_SEL_LBS_0,
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FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC0_0,
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FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3, FN_SEL_LBS_0,
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FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0,
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FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, FN_SEL_RCN_0,
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FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0,
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@ -379,8 +379,8 @@ enum {
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D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK,
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D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK,
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D13_MARK, SCIFA1_SCK_MARK, TANS1_MARK, PWM2_C_MARK, TCLK2_B_MARK,
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D14_MARK, SCIFA1_RXD_MARK, IIC0_SCL_B_MARK, D15_MARK, SCIFA1_TXD_MARK,
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IIC0_SDA_B_MARK, A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK, A1_MARK,
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D14_MARK, SCIFA1_RXD_MARK, I2C5_SCL_B_MARK, D15_MARK, SCIFA1_TXD_MARK,
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I2C5_SDA_B_MARK, A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK, A1_MARK,
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SCIFB1_TXD_MARK, A3_MARK, SCIFB0_SCK_MARK, A4_MARK, SCIFB0_TXD_MARK,
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A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK, A6_MARK,
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SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK,
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@ -388,8 +388,8 @@ enum {
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/* IPSR2 */
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A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK, A8_MARK, MSIOF1_RXD_MARK,
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SCIFA0_RXD_B_MARK, A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK,
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A10_MARK, MSIOF1_SCK_MARK, IIC1_SCL_B_MARK, A11_MARK, MSIOF1_SYNC_MARK,
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IIC1_SDA_B_MARK, A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK,
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A10_MARK, MSIOF1_SCK_MARK, IIC0_SCL_B_MARK, A11_MARK, MSIOF1_SYNC_MARK,
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IIC0_SDA_B_MARK, A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK,
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A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK, A14_MARK, MSIOF2_RXD_MARK,
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HSCIF0_HRX_B_MARK, DREQ1_N_MARK, A15_MARK, MSIOF2_TXD_MARK,
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HSCIF0_HTX_B_MARK, DACK1_MARK, A16_MARK, MSIOF2_SCK_MARK,
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@ -464,11 +464,11 @@ enum {
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AVB_RX_ER_MARK, VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK,
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IERX_C_MARK, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK,
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I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK,
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VI0_G0_MARK, MSIOF2_RXD_B_MARK, IIC0_SCL_D_MARK, AVB_TX_CLK_MARK,
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VI0_G0_MARK, MSIOF2_RXD_B_MARK, I2C5_SCL_D_MARK, AVB_TX_CLK_MARK,
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ADIDATA_MARK, AD_DI_MARK,
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/* IPSR7 */
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ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, IIC0_SDA_D_MARK,
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ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, I2C5_SDA_D_MARK,
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AVB_TXD0_MARK, ADICS_SAMP_MARK, AD_DO_MARK, ETH_RX_ER_MARK, VI0_G2_MARK,
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MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, ADICLK_MARK,
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AD_CLK_MARK, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK,
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@ -478,8 +478,8 @@ enum {
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MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, AVB_TXD4_MARK, ADICHS2_MARK,
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ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
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SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK,
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IIC1_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK,
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VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC1_SDA_D_MARK, AVB_TXD7_MARK,
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IIC0_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK,
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VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC0_SDA_D_MARK, AVB_TXD7_MARK,
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SSI_SDATA5_B_MARK, ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK,
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AVB_TX_ER_MARK, SSI_SCK6_B_MARK, ETH_TXD0_MARK, VI0_R2_MARK,
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SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
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@ -525,12 +525,12 @@ enum {
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CAN_TXCLK_MARK, CC50_STATE34_MARK,
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/* IPSR10 */
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SCIF1_RXD_MARK, IIC0_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK,
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CAN_DEBUGOUT0_MARK, CC50_STATE35_MARK, SCIF1_TXD_MARK, IIC0_SDA_MARK,
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SCIF1_RXD_MARK, I2C5_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK,
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CAN_DEBUGOUT0_MARK, CC50_STATE35_MARK, SCIF1_TXD_MARK, I2C5_SDA_MARK,
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DU1_DG7_MARK, SSI_WS2_B_MARK, CAN_DEBUGOUT1_MARK, CC50_STATE36_MARK,
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SCIF2_RXD_MARK, IIC1_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
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SCIF2_RXD_MARK, IIC0_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
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USB0_EXTLP_MARK, CAN_DEBUGOUT2_MARK, CC50_STATE37_MARK, SCIF2_TXD_MARK,
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IIC1_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK, USB0_OVC1_MARK,
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IIC0_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK, USB0_OVC1_MARK,
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CAN_DEBUGOUT3_MARK, CC50_STATE38_MARK, SCIF2_SCK_MARK, IRQ1_MARK,
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DU1_DB2_MARK, SSI_WS9_B_MARK, USB0_IDIN_MARK, CAN_DEBUGOUT4_MARK,
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CC50_STATE39_MARK, SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK,
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@ -552,8 +552,8 @@ enum {
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SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
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DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK, SSI_SDATA6_MARK,
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SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
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CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, IIC0_SDA_C_MARK,
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DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, IIC0_SCL_C_MARK,
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CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, I2C5_SDA_C_MARK,
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DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, I2C5_SCL_C_MARK,
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DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK,
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AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, PCMOE_N_MARK, SSI_SCK0129_MARK,
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MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, AD_DI_B_MARK,
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@ -571,8 +571,8 @@ enum {
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SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK, IRD_SCK_MARK,
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SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK,
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DACK2_MARK, ETH_MDIO_B_MARK, SSI_SCK1_MARK, SCIF1_RXD_B_MARK,
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IIC1_SCL_C_MARK, VI1_CLK_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_MARK,
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ETH_CRS_DV_B_MARK, SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC1_SDA_C_MARK,
|
||||
IIC0_SCL_C_MARK, VI1_CLK_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_MARK,
|
||||
ETH_CRS_DV_B_MARK, SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC0_SDA_C_MARK,
|
||||
VI1_DATA0_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_MARK, ETH_RX_ER_B_MARK,
|
||||
SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, SDATA_MARK,
|
||||
ATAWR0_N_MARK, ETH_RXD0_B_MARK, SSI_SCK2_MARK, HSCIF1_HTX_B_MARK,
|
||||
|
|
@ -705,10 +705,10 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1),
|
||||
PINMUX_IPSR_GPSR(IP1_19_18, D14),
|
||||
PINMUX_IPSR_MSEL(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0),
|
||||
PINMUX_IPSR_MSEL(IP1_19_18, IIC0_SCL_B, SEL_IIC00_1),
|
||||
PINMUX_IPSR_MSEL(IP1_19_18, I2C5_SCL_B, SEL_I2C05_1),
|
||||
PINMUX_IPSR_GPSR(IP1_21_20, D15),
|
||||
PINMUX_IPSR_MSEL(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0),
|
||||
PINMUX_IPSR_MSEL(IP1_21_20, IIC0_SDA_B, SEL_IIC00_1),
|
||||
PINMUX_IPSR_MSEL(IP1_21_20, I2C5_SDA_B, SEL_I2C05_1),
|
||||
PINMUX_IPSR_GPSR(IP1_23_22, A0),
|
||||
PINMUX_IPSR_GPSR(IP1_23_22, SCIFB1_SCK),
|
||||
PINMUX_IPSR_GPSR(IP1_23_22, PWM3_B),
|
||||
|
|
@ -739,10 +739,10 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1),
|
||||
PINMUX_IPSR_GPSR(IP2_7_6, A10),
|
||||
PINMUX_IPSR_MSEL(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0),
|
||||
PINMUX_IPSR_MSEL(IP2_7_6, IIC1_SCL_B, SEL_IIC01_1),
|
||||
PINMUX_IPSR_MSEL(IP2_7_6, IIC0_SCL_B, SEL_IIC0_1),
|
||||
PINMUX_IPSR_GPSR(IP2_9_8, A11),
|
||||
PINMUX_IPSR_MSEL(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0),
|
||||
PINMUX_IPSR_MSEL(IP2_9_8, IIC1_SDA_B, SEL_IIC01_1),
|
||||
PINMUX_IPSR_MSEL(IP2_9_8, IIC0_SDA_B, SEL_IIC0_1),
|
||||
PINMUX_IPSR_GPSR(IP2_11_10, A12),
|
||||
PINMUX_IPSR_MSEL(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0),
|
||||
PINMUX_IPSR_MSEL(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1),
|
||||
|
|
@ -1014,7 +1014,7 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP6_31_29, ETH_MDIO, SEL_ETH_0),
|
||||
PINMUX_IPSR_GPSR(IP6_31_29, VI0_G0),
|
||||
PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
|
||||
PINMUX_IPSR_MSEL(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3),
|
||||
PINMUX_IPSR_MSEL(IP6_31_29, I2C5_SCL_D, SEL_I2C05_3),
|
||||
PINMUX_IPSR_GPSR(IP6_31_29, AVB_TX_CLK),
|
||||
PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0),
|
||||
PINMUX_IPSR_MSEL(IP6_31_29, AD_DI, SEL_ADI_0),
|
||||
|
|
@ -1023,7 +1023,7 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
|
||||
PINMUX_IPSR_GPSR(IP7_2_0, VI0_G1),
|
||||
PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
|
||||
PINMUX_IPSR_MSEL(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3),
|
||||
PINMUX_IPSR_MSEL(IP7_2_0, I2C5_SDA_D, SEL_I2C05_3),
|
||||
PINMUX_IPSR_GPSR(IP7_2_0, AVB_TXD0),
|
||||
PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
|
||||
PINMUX_IPSR_MSEL(IP7_2_0, AD_DO, SEL_ADI_0),
|
||||
|
|
@ -1061,13 +1061,13 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP7_20_18, ETH_TXD1, SEL_ETH_0),
|
||||
PINMUX_IPSR_GPSR(IP7_20_18, VI0_G7),
|
||||
PINMUX_IPSR_MSEL(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
|
||||
PINMUX_IPSR_MSEL(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3),
|
||||
PINMUX_IPSR_MSEL(IP7_20_18, IIC0_SCL_D, SEL_IIC0_3),
|
||||
PINMUX_IPSR_GPSR(IP7_20_18, AVB_TXD6),
|
||||
PINMUX_IPSR_MSEL(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
|
||||
PINMUX_IPSR_MSEL(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
|
||||
PINMUX_IPSR_GPSR(IP7_23_21, VI0_R0),
|
||||
PINMUX_IPSR_MSEL(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
|
||||
PINMUX_IPSR_MSEL(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3),
|
||||
PINMUX_IPSR_MSEL(IP7_23_21, IIC0_SDA_D, SEL_IIC0_3),
|
||||
PINMUX_IPSR_GPSR(IP7_23_21, AVB_TXD7),
|
||||
PINMUX_IPSR_MSEL(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
|
||||
PINMUX_IPSR_MSEL(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
|
||||
|
|
@ -1229,26 +1229,26 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
/* IPSR10 */
|
||||
PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0),
|
||||
PINMUX_IPSR_MSEL(IP10_2_0, IIC0_SCL, SEL_IIC00_0),
|
||||
PINMUX_IPSR_MSEL(IP10_2_0, I2C5_SCL, SEL_I2C05_0),
|
||||
PINMUX_IPSR_GPSR(IP10_2_0, DU1_DG6),
|
||||
PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1),
|
||||
PINMUX_IPSR_GPSR(IP10_2_0, CAN_DEBUGOUT0),
|
||||
PINMUX_IPSR_GPSR(IP10_2_0, CC50_STATE35),
|
||||
PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0),
|
||||
PINMUX_IPSR_MSEL(IP10_5_3, IIC0_SDA, SEL_IIC00_0),
|
||||
PINMUX_IPSR_MSEL(IP10_5_3, I2C5_SDA, SEL_I2C05_0),
|
||||
PINMUX_IPSR_GPSR(IP10_5_3, DU1_DG7),
|
||||
PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1),
|
||||
PINMUX_IPSR_GPSR(IP10_5_3, CAN_DEBUGOUT1),
|
||||
PINMUX_IPSR_GPSR(IP10_5_3, CC50_STATE36),
|
||||
PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0),
|
||||
PINMUX_IPSR_MSEL(IP10_8_6, IIC1_SCL, SEL_IIC01_0),
|
||||
PINMUX_IPSR_MSEL(IP10_8_6, IIC0_SCL, SEL_IIC0_0),
|
||||
PINMUX_IPSR_GPSR(IP10_8_6, DU1_DB0),
|
||||
PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1),
|
||||
PINMUX_IPSR_GPSR(IP10_8_6, USB0_EXTLP),
|
||||
PINMUX_IPSR_GPSR(IP10_8_6, CAN_DEBUGOUT2),
|
||||
PINMUX_IPSR_GPSR(IP10_8_6, CC50_STATE37),
|
||||
PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0),
|
||||
PINMUX_IPSR_MSEL(IP10_11_9, IIC1_SDA, SEL_IIC01_0),
|
||||
PINMUX_IPSR_MSEL(IP10_11_9, IIC0_SDA, SEL_IIC0_0),
|
||||
PINMUX_IPSR_GPSR(IP10_11_9, DU1_DB1),
|
||||
PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1),
|
||||
PINMUX_IPSR_GPSR(IP10_11_9, USB0_OVC1),
|
||||
|
|
@ -1328,11 +1328,11 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_GPSR(IP11_13_11, CAN_DEBUGOUT15),
|
||||
PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
|
||||
PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
|
||||
PINMUX_IPSR_MSEL(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2),
|
||||
PINMUX_IPSR_MSEL(IP11_15_14, I2C5_SDA_C, SEL_I2C05_2),
|
||||
PINMUX_IPSR_GPSR(IP11_15_14, DU1_DISP),
|
||||
PINMUX_IPSR_MSEL(IP11_17_16, SSI_WS78, SEL_SSI7_0),
|
||||
PINMUX_IPSR_MSEL(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
|
||||
PINMUX_IPSR_MSEL(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2),
|
||||
PINMUX_IPSR_MSEL(IP11_17_16, I2C5_SCL_C, SEL_I2C05_2),
|
||||
PINMUX_IPSR_GPSR(IP11_17_16, DU1_CDE),
|
||||
PINMUX_IPSR_MSEL(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
|
||||
PINMUX_IPSR_MSEL(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
|
||||
|
|
@ -1397,14 +1397,14 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1),
|
||||
PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0),
|
||||
PINMUX_IPSR_MSEL(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1),
|
||||
PINMUX_IPSR_MSEL(IP12_20_18, IIC1_SCL_C, SEL_IIC01_2),
|
||||
PINMUX_IPSR_MSEL(IP12_20_18, IIC0_SCL_C, SEL_IIC0_2),
|
||||
PINMUX_IPSR_GPSR(IP12_20_18, VI1_CLK),
|
||||
PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3),
|
||||
PINMUX_IPSR_MSEL(IP12_20_18, AVB_AVTP_CAPTURE, SEL_AVB_0),
|
||||
PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1),
|
||||
PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0),
|
||||
PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1),
|
||||
PINMUX_IPSR_MSEL(IP12_23_21, IIC1_SDA_C, SEL_IIC01_2),
|
||||
PINMUX_IPSR_MSEL(IP12_23_21, IIC0_SDA_C, SEL_IIC0_2),
|
||||
PINMUX_IPSR_GPSR(IP12_23_21, VI1_DATA0),
|
||||
PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3),
|
||||
PINMUX_IPSR_MSEL(IP12_23_21, AVB_AVTP_MATCH, SEL_AVB_0),
|
||||
|
|
@ -4540,9 +4540,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
/* IP1_23_22 [2] */
|
||||
FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 0,
|
||||
/* IP1_21_20 [2] */
|
||||
FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B, 0,
|
||||
FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B, 0,
|
||||
/* IP1_19_18 [2] */
|
||||
FN_D14, FN_SCIFA1_RXD, FN_IIC0_SCL_B, 0,
|
||||
FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B, 0,
|
||||
/* IP1_17_15 [3] */
|
||||
FN_D13, FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B,
|
||||
0, 0, 0,
|
||||
|
|
@ -4587,9 +4587,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
/* IP2_11_10 [2] */
|
||||
FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 0,
|
||||
/* IP2_9_8 [2] */
|
||||
FN_A11, FN_MSIOF1_SYNC, FN_IIC1_SDA_B, 0,
|
||||
FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B, 0,
|
||||
/* IP2_7_6 [2] */
|
||||
FN_A10, FN_MSIOF1_SCK, FN_IIC1_SCL_B, 0,
|
||||
FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B, 0,
|
||||
/* IP2_5_4 [2] */
|
||||
FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 0,
|
||||
/* IP2_3_2 [2] */
|
||||
|
|
@ -4711,7 +4711,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
|
||||
2, 2) {
|
||||
/* IP6_31_29 [3] */
|
||||
FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D,
|
||||
FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D,
|
||||
FN_AVB_TX_CLK, FN_ADIDATA, FN_AD_DI, 0,
|
||||
/* IP6_28_26 [3] */
|
||||
FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C,
|
||||
|
|
@ -4766,10 +4766,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER,
|
||||
FN_SSI_SCK6_B, 0, 0, 0,
|
||||
/* IP7_23_21 [3] */
|
||||
FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC1_SDA_D,
|
||||
FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D,
|
||||
FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0,
|
||||
/* IP7_20_18 [3] */
|
||||
FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC1_SCL_D,
|
||||
FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D,
|
||||
FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0,
|
||||
/* IP7_17_15 [3] */
|
||||
FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5,
|
||||
|
|
@ -4787,7 +4787,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B,
|
||||
FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, 0,
|
||||
/* IP7_2_0 [3] */
|
||||
FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D,
|
||||
FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D,
|
||||
FN_AVB_TXD0, FN_ADICS_SAMP, FN_AD_DO, 0, }
|
||||
},
|
||||
{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
|
||||
|
|
@ -4884,16 +4884,16 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
|
||||
FN_USB0_IDIN, FN_CAN_DEBUGOUT4, FN_CC50_STATE39, 0,
|
||||
/* IP10_11_9 [3] */
|
||||
FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
|
||||
FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
|
||||
FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, 0,
|
||||
/* IP10_8_6 [3] */
|
||||
FN_SCIF2_RXD, FN_IIC1_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
|
||||
FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
|
||||
FN_USB0_EXTLP, FN_CAN_DEBUGOUT2, FN_CC50_STATE37, 0,
|
||||
/* IP10_5_3 [3] */
|
||||
FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
|
||||
FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
|
||||
FN_CAN_DEBUGOUT1, FN_CC50_STATE36, 0, 0,
|
||||
/* IP10_2_0 [3] */
|
||||
FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
|
||||
FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
|
||||
FN_CAN_DEBUGOUT0, FN_CC50_STATE35, 0, 0, }
|
||||
},
|
||||
{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
|
||||
|
|
@ -4913,9 +4913,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D,
|
||||
FN_CAN_CLK_D, FN_PCMOE_N, 0, 0,
|
||||
/* IP11_17_16 [2] */
|
||||
FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE,
|
||||
FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
|
||||
/* IP11_15_14 [2] */
|
||||
FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP,
|
||||
FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
|
||||
/* IP11_13_11 [3] */
|
||||
FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
|
||||
FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, 0, 0, 0,
|
||||
|
|
@ -4943,10 +4943,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_SDATA,
|
||||
FN_ATAWR0_N, FN_ETH_RXD0_B, 0, 0,
|
||||
/* IP12_23_21 [3] */
|
||||
FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC1_SDA_C, FN_VI1_DATA0,
|
||||
FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0,
|
||||
FN_CAN0_TX_D, FN_AVB_AVTP_MATCH, FN_ETH_RX_ER_B, 0,
|
||||
/* IP12_20_18 [3] */
|
||||
FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK,
|
||||
FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK,
|
||||
FN_CAN0_RX_D, FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, 0,
|
||||
/* IP12_17_15 [3] */
|
||||
FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9,
|
||||
|
|
@ -5046,8 +5046,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
/* SEL_I2C04 [3] */
|
||||
FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
|
||||
FN_SEL_I2C04_4, 0, 0, 0,
|
||||
/* SEL_IIC00 [2] */
|
||||
FN_SEL_IIC00_0, FN_SEL_IIC00_1, FN_SEL_IIC00_2, FN_SEL_IIC00_3,
|
||||
/* SEL_I2C05 [2] */
|
||||
FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
|
||||
/* SEL_AVB [1] */
|
||||
FN_SEL_AVB_0, FN_SEL_AVB_1, }
|
||||
},
|
||||
|
|
@ -5057,7 +5057,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
/* SEL_IEB [2] */
|
||||
FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
|
||||
/* SEL_IIC0 [2] */
|
||||
FN_SEL_IIC01_0, FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3,
|
||||
FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3,
|
||||
/* SEL_LBS [1] */
|
||||
FN_SEL_LBS_0, FN_SEL_LBS_1,
|
||||
/* SEL_MSI1 [1] */
|
||||
|
|
|
|||
Loading…
Reference in New Issue