drm/amd/powerplay: fix pcie max lane define error
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -297,7 +297,7 @@ typedef enum PP_PCIEGen PP_PCIEGen;
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#define PP_Min_PCIEGen PP_PCIEGen1
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#define PP_Max_PCIEGen PP_PCIEGen3
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#define PP_Min_PCIELane 1
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#define PP_Max_PCIELane 32
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#define PP_Max_PCIELane 16
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enum phm_clock_Type {
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PHM_DispClock = 1,
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