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drm/i915: Move the .global_resources() hook call into modeset_update_crtc_power_domains() 

We may need to access various hardware bits in the .global_resources()
hook, so move the call to occur after enabling all the newly required
power wells, but before disabling all the now unneeded wells. This
should guarantee that we have all the sufficient hardware resources
available during the .global_resources() call. And if not, any additional
resources must be explicitly acquired by the .global_resorces() hook.

For instance on VLV/CHV we need to access the gunit mailbox so that we
can talk to punit/cck over sideband. In addition some PFI credit
reprogramming may need to be addes as well, which may require the disp2d
well.

This should also make the power domain refcounts consistent on platforms
which don't have a .global_resource() hook since now they too will
call modeset_update_crtc_power_domains() which will drop the init power.
Previously init power was just left enabled for such platforms.

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2014-11-06 14:49:12 +02:00 committed by Daniel Vetter
parent 28855d2ac3
commit 50f6e50271
1 changed files with 4 additions and 21 deletions
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25
drivers/gpu/drm/i915/intel_display.c
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@ -4683,6 +4683,9 @@ static void modeset_update_crtc_power_domains(struct drm_device *dev)
intel_display_power_get(dev_priv, domain);
}
if (dev_priv->display.modeset_global_resources)
dev_priv->display.modeset_global_resources(dev);
for_each_intel_crtc(dev, crtc) {
enum intel_display_power_domain domain;
@ -4910,8 +4913,6 @@ static void valleyview_modeset_global_resources(struct drm_device *dev)
else
valleyview_set_cdclk(dev, req_cdclk);
}
modeset_update_crtc_power_domains(dev);
}
static void valleyview_crtc_enable(struct drm_crtc *crtc)
@ -7950,16 +7951,6 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
intel_prepare_ddi(dev);
}
static void snb_modeset_global_resources(struct drm_device *dev)
{
modeset_update_crtc_power_domains(dev);
}
static void haswell_modeset_global_resources(struct drm_device *dev)
{
modeset_update_crtc_power_domains(dev);
}
static int haswell_crtc_compute_clock(struct intel_crtc *crtc)
{
if (!intel_ddi_pll_select(crtc))
@ -10917,8 +10908,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
* update the the output configuration. */
intel_modeset_update_state(dev, prepare_pipes);
if (dev_priv->display.modeset_global_resources)
dev_priv->display.modeset_global_resources(dev);
modeset_update_crtc_power_domains(dev);
/* Set up the DPLL and any encoders state that needs to adjust or depend
* on the DPLL.
@ -12589,8 +12579,6 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
} else if (IS_GEN6(dev)) {
dev_priv->display.fdi_link_train = gen6_fdi_link_train;
dev_priv->display.modeset_global_resources =
snb_modeset_global_resources;
} else if (IS_IVYBRIDGE(dev)) {
/* FIXME: detect B0+ stepping and use auto training */
dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
@ -12598,14 +12586,9 @@ static void intel_init_display(struct drm_device *dev)
ivb_modeset_global_resources;
} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
dev_priv->display.fdi_link_train = hsw_fdi_link_train;
dev_priv->display.modeset_global_resources =
haswell_modeset_global_resources;
} else if (IS_VALLEYVIEW(dev)) {
dev_priv->display.modeset_global_resources =
valleyview_modeset_global_resources;
} else if (INTEL_INFO(dev)->gen >= 9) {
dev_priv->display.modeset_global_resources =
haswell_modeset_global_resources;
}
/* Default just returns -ENODEV to indicate unsupported */