drm/virtio: implement blob resources: fix stride discrepancy
The old transfer ioctls may work on blob resources, and there is no TRANSFER_BLOB hypercall now for simplicity. The guest may have a image view on the blob resources such that the stride is not equal to width * bytes_per_pixel. For host-only blobs, we can repurpose the transfer ioctls to synchronize caches as well. For guest-only blobs, these operations are undefined for now so leave them out. Also, with seamless Wayland integration between guest/host looking increasingly attractive, it also makes sense to keep track of one value for stride. Signed-off-by: Gurchetan Singh <gurchetansingh@chromium.org> Acked-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Link: http://patchwork.freedesktop.org/patch/msgid/20200924003214.662-16-gurchetansingh@chromium.org Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
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1e2554f49e
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50c3d1938e
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@ -351,12 +351,16 @@ void virtio_gpu_cmd_submit(struct virtio_gpu_device *vgdev,
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void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev,
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uint32_t ctx_id,
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uint64_t offset, uint32_t level,
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uint32_t stride,
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uint32_t layer_stride,
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struct drm_virtgpu_3d_box *box,
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struct virtio_gpu_object_array *objs,
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struct virtio_gpu_fence *fence);
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void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
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uint32_t ctx_id,
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uint64_t offset, uint32_t level,
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uint32_t stride,
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uint32_t layer_stride,
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struct drm_virtgpu_3d_box *box,
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struct virtio_gpu_object_array *objs,
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struct virtio_gpu_fence *fence);
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@ -312,6 +312,7 @@ static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev,
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struct virtio_gpu_device *vgdev = dev->dev_private;
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struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
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struct drm_virtgpu_3d_transfer_from_host *args = data;
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struct virtio_gpu_object *bo;
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struct virtio_gpu_object_array *objs;
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struct virtio_gpu_fence *fence;
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int ret;
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@ -325,6 +326,17 @@ static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev,
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if (objs == NULL)
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return -ENOENT;
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bo = gem_to_virtio_gpu_obj(objs->objs[0]);
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if (bo->guest_blob && !bo->host3d_blob) {
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ret = -EINVAL;
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goto err_put_free;
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}
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if (!bo->host3d_blob && (args->stride || args->layer_stride)) {
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ret = -EINVAL;
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goto err_put_free;
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}
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ret = virtio_gpu_array_lock_resv(objs);
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if (ret != 0)
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goto err_put_free;
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@ -334,9 +346,10 @@ static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev,
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ret = -ENOMEM;
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goto err_unlock;
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}
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virtio_gpu_cmd_transfer_from_host_3d
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(vgdev, vfpriv->ctx_id, offset, args->level,
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&args->box, objs, fence);
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(vgdev, vfpriv->ctx_id, offset, args->level, args->stride,
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args->layer_stride, &args->box, objs, fence);
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dma_fence_put(&fence->f);
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virtio_gpu_notify(vgdev);
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return 0;
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@ -354,6 +367,7 @@ static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data,
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struct virtio_gpu_device *vgdev = dev->dev_private;
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struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
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struct drm_virtgpu_3d_transfer_to_host *args = data;
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struct virtio_gpu_object *bo;
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struct virtio_gpu_object_array *objs;
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struct virtio_gpu_fence *fence;
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int ret;
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@ -363,6 +377,12 @@ static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data,
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if (objs == NULL)
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return -ENOENT;
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bo = gem_to_virtio_gpu_obj(objs->objs[0]);
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if (bo->guest_blob && !bo->host3d_blob) {
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ret = -EINVAL;
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goto err_put_free;
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}
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if (!vgdev->has_virgl_3d) {
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virtio_gpu_cmd_transfer_to_host_2d
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(vgdev, offset,
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@ -370,6 +390,12 @@ static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data,
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objs, NULL);
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} else {
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virtio_gpu_create_context(dev, file);
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if (!bo->host3d_blob && (args->stride || args->layer_stride)) {
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ret = -EINVAL;
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goto err_put_free;
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}
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ret = virtio_gpu_array_lock_resv(objs);
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if (ret != 0)
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goto err_put_free;
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@ -381,8 +407,9 @@ static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data,
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virtio_gpu_cmd_transfer_to_host_3d
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(vgdev,
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vfpriv ? vfpriv->ctx_id : 0, offset,
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args->level, &args->box, objs, fence);
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vfpriv ? vfpriv->ctx_id : 0, offset, args->level,
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args->stride, args->layer_stride, &args->box, objs,
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fence);
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dma_fence_put(&fence->f);
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}
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virtio_gpu_notify(vgdev);
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@ -1017,6 +1017,8 @@ virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev,
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void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
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uint32_t ctx_id,
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uint64_t offset, uint32_t level,
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uint32_t stride,
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uint32_t layer_stride,
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struct drm_virtgpu_3d_box *box,
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struct virtio_gpu_object_array *objs,
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struct virtio_gpu_fence *fence)
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@ -1025,12 +1027,14 @@ void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
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struct virtio_gpu_transfer_host_3d *cmd_p;
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struct virtio_gpu_vbuffer *vbuf;
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bool use_dma_api = !virtio_has_dma_quirk(vgdev->vdev);
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struct virtio_gpu_object_shmem *shmem = to_virtio_gpu_shmem(bo);
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if (use_dma_api)
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if (virtio_gpu_is_shmem(bo) && use_dma_api) {
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struct virtio_gpu_object_shmem *shmem = to_virtio_gpu_shmem(bo);
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dma_sync_sg_for_device(vgdev->vdev->dev.parent,
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shmem->pages->sgl, shmem->pages->nents,
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DMA_TO_DEVICE);
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}
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cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
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memset(cmd_p, 0, sizeof(*cmd_p));
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@ -1043,6 +1047,8 @@ void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
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convert_to_hw_box(&cmd_p->box, box);
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cmd_p->offset = cpu_to_le64(offset);
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cmd_p->level = cpu_to_le32(level);
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cmd_p->stride = cpu_to_le32(stride);
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cmd_p->layer_stride = cpu_to_le32(layer_stride);
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virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
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}
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@ -1050,6 +1056,8 @@ void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
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void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev,
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uint32_t ctx_id,
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uint64_t offset, uint32_t level,
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uint32_t stride,
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uint32_t layer_stride,
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struct drm_virtgpu_3d_box *box,
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struct virtio_gpu_object_array *objs,
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struct virtio_gpu_fence *fence)
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@ -1069,6 +1077,8 @@ void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev,
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convert_to_hw_box(&cmd_p->box, box);
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cmd_p->offset = cpu_to_le64(offset);
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cmd_p->level = cpu_to_le32(level);
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cmd_p->stride = cpu_to_le32(stride);
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cmd_p->layer_stride = cpu_to_le32(layer_stride);
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virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
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}
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