i40e/i40evf: i40e_register.h updates
Some registers have been removed so take them out and stop updating and looking at them. Change-ID: I33da922c8de993a94dd8b8d8a2ae2146b8ca1a27 Signed-off-by: Anjali Singhai Jain <anjali.singhai@intel.com> Tested-by: Jim Young <james.m.young@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Anjali Singhai Jain
Jeff Kirsher
parent
2b18e5914d
commit
5098850c9b
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@ -113,7 +113,6 @@ static struct i40e_stats i40e_gstrings_stats[] = {
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I40E_PF_STAT("tx_broadcast", stats.eth.tx_broadcast),
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I40E_PF_STAT("tx_errors", stats.eth.tx_errors),
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I40E_PF_STAT("rx_dropped", stats.eth.rx_discards),
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I40E_PF_STAT("tx_dropped", stats.eth.tx_discards),
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I40E_PF_STAT("tx_dropped_link_down", stats.tx_dropped_link_down),
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I40E_PF_STAT("crc_errors", stats.crc_errors),
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I40E_PF_STAT("illegal_bytes", stats.illegal_bytes),
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@ -919,11 +919,6 @@ static void i40e_update_pf_stats(struct i40e_pf *pf)
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pf->stat_offsets_loaded,
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&osd->eth.rx_discards,
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&nsd->eth.rx_discards);
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i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
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pf->stat_offsets_loaded,
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&osd->eth.tx_discards,
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&nsd->eth.tx_discards);
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i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
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I40E_GLPRT_UPRCL(hw->port),
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pf->stat_offsets_loaded,
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@ -5042,24 +5037,6 @@ void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
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wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
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i40e_flush(&pf->hw);
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} else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
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/* Request a Firmware Reset
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*
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* Same as Global reset, plus restarting the
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* embedded firmware engine.
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*/
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/* enable EMP Reset */
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val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
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val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
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wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
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/* force the reset */
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val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
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val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
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wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
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i40e_flush(&pf->hw);
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} else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
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/* Request a PF Reset
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@ -310,6 +310,10 @@
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#define I40E_PRTDCB_RUP2TC_UP6TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP6TC_SHIFT)
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#define I40E_PRTDCB_RUP2TC_UP7TC_SHIFT 21
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#define I40E_PRTDCB_RUP2TC_UP7TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP7TC_SHIFT)
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#define I40E_PRTDCB_RUPTQ(_i) (0x00122400 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
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#define I40E_PRTDCB_RUPTQ_MAX_INDEX 7
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#define I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT 0
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#define I40E_PRTDCB_RUPTQ_RXQNUM_MASK I40E_MASK(0x3FFF, I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT)
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#define I40E_PRTDCB_TC2PFC 0x001C0980 /* Reset: CORER */
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#define I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT 0
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#define I40E_PRTDCB_TC2PFC_TC2PFC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT)
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@ -421,6 +425,8 @@
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#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT)
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#define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT 20
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#define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_MASK I40E_MASK(0x3F, I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT)
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#define I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_SHIFT 26
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#define I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_MASK I40E_MASK(0xF, I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_SHIFT)
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#define I40E_GLGEN_GPIO_SET 0x00088184 /* Reset: POR */
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#define I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT 0
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#define I40E_GLGEN_GPIO_SET_GPIO_INDX_MASK I40E_MASK(0x1F, I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT)
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@ -484,7 +490,9 @@
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#define I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT 17
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#define I40E_GLGEN_MDIO_CTRL_CONTMDC_MASK I40E_MASK(0x1, I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT)
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#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT 18
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#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_MASK I40E_MASK(0x3FFF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT)
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#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_MASK I40E_MASK(0x7FF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT)
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#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_SHIFT 29
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#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_MASK I40E_MASK(0x7, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_SHIFT)
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#define I40E_GLGEN_MDIO_I2C_SEL(_i) (0x000881C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
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#define I40E_GLGEN_MDIO_I2C_SEL_MAX_INDEX 3
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#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT 0
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@ -548,9 +556,6 @@
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#define I40E_GLGEN_RSTCTL_GRSTDEL_MASK I40E_MASK(0x3F, I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT)
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#define I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT 8
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#define I40E_GLGEN_RSTCTL_ECC_RST_ENA_MASK I40E_MASK(0x1, I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT)
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#define I40E_GLGEN_RSTENA_EMP 0x000B818C /* Reset: POR */
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#define I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_SHIFT 0
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#define I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK I40E_MASK(0x1, I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_SHIFT)
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#define I40E_GLGEN_RTRIG 0x000B8190 /* Reset: CORER */
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#define I40E_GLGEN_RTRIG_CORER_SHIFT 0
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#define I40E_GLGEN_RTRIG_CORER_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_CORER_SHIFT)
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@ -1066,7 +1071,7 @@
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#define I40E_PFINT_RATEN_INTERVAL_MASK I40E_MASK(0x3F, I40E_PFINT_RATEN_INTERVAL_SHIFT)
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#define I40E_PFINT_RATEN_INTRL_ENA_SHIFT 6
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#define I40E_PFINT_RATEN_INTRL_ENA_MASK I40E_MASK(0x1, I40E_PFINT_RATEN_INTRL_ENA_SHIFT)
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#define I40E_PFINT_STAT_CTL0 0x00038400 /* Reset: PFR */
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#define I40E_PFINT_STAT_CTL0 0x00038400 /* Reset: CORER */
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#define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2
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#define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT)
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#define I40E_QINT_RQCTL(_Q) (0x0003A000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
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@ -1171,7 +1176,7 @@
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#define I40E_VFINT_ITRN_MAX_INDEX 2
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#define I40E_VFINT_ITRN_INTERVAL_SHIFT 0
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#define I40E_VFINT_ITRN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN_INTERVAL_SHIFT)
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#define I40E_VFINT_STAT_CTL0(_VF) (0x0002A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
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#define I40E_VFINT_STAT_CTL0(_VF) (0x0002A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
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#define I40E_VFINT_STAT_CTL0_MAX_INDEX 127
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#define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2
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#define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT)
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@ -1803,9 +1808,6 @@
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#define I40E_GLPCI_GSCN_0_3_MAX_INDEX 3
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#define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT 0
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#define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT)
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#define I40E_GLPCI_LATCT 0x0009C4B4 /* Reset: PCIR */
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#define I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_SHIFT 0
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#define I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_SHIFT)
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#define I40E_GLPCI_LBARCTRL 0x000BE484 /* Reset: POR */
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#define I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT 0
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#define I40E_GLPCI_LBARCTRL_PREFBAR_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT)
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@ -1902,6 +1904,11 @@
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#define I40E_GLPCI_VFSUP_VF_PREFETCH_MASK I40E_MASK(0x1, I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT)
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#define I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT 1
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#define I40E_GLPCI_VFSUP_VR_BAR_TYPE_MASK I40E_MASK(0x1, I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT)
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#define I40E_GLTPH_CTRL 0x000BE480 /* Reset: PCIR */
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#define I40E_GLTPH_CTRL_DESC_PH_SHIFT 9
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#define I40E_GLTPH_CTRL_DESC_PH_MASK I40E_MASK(0x3, I40E_GLTPH_CTRL_DESC_PH_SHIFT)
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#define I40E_GLTPH_CTRL_DATA_PH_SHIFT 11
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#define I40E_GLTPH_CTRL_DATA_PH_MASK I40E_MASK(0x3, I40E_GLTPH_CTRL_DATA_PH_SHIFT)
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#define I40E_PF_FUNC_RID 0x0009C000 /* Reset: PCIR */
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#define I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT 0
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#define I40E_PF_FUNC_RID_FUNCTION_NUMBER_MASK I40E_MASK(0x7, I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT)
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@ -2374,20 +2381,20 @@
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#define I40E_GL_RXERR2_L_FCOEDIXAC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR2_L_FCOEDIXAC_SHIFT)
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#define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
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#define I40E_GLPRT_BPRCH_MAX_INDEX 3
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#define I40E_GLPRT_BPRCH_UPRCH_SHIFT 0
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#define I40E_GLPRT_BPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPRCH_UPRCH_SHIFT)
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#define I40E_GLPRT_BPRCH_BPRCH_SHIFT 0
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#define I40E_GLPRT_BPRCH_BPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPRCH_BPRCH_SHIFT)
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#define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
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#define I40E_GLPRT_BPRCL_MAX_INDEX 3
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#define I40E_GLPRT_BPRCL_UPRCH_SHIFT 0
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#define I40E_GLPRT_BPRCL_UPRCH_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPRCL_UPRCH_SHIFT)
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#define I40E_GLPRT_BPRCL_BPRCL_SHIFT 0
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#define I40E_GLPRT_BPRCL_BPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPRCL_BPRCL_SHIFT)
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#define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
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#define I40E_GLPRT_BPTCH_MAX_INDEX 3
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#define I40E_GLPRT_BPTCH_UPRCH_SHIFT 0
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#define I40E_GLPRT_BPTCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPTCH_UPRCH_SHIFT)
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#define I40E_GLPRT_BPTCH_BPTCH_SHIFT 0
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#define I40E_GLPRT_BPTCH_BPTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPTCH_BPTCH_SHIFT)
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#define I40E_GLPRT_BPTCL(_i) (0x00300A00 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
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#define I40E_GLPRT_BPTCL_MAX_INDEX 3
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#define I40E_GLPRT_BPTCL_UPRCH_SHIFT 0
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#define I40E_GLPRT_BPTCL_UPRCH_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPTCL_UPRCH_SHIFT)
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#define I40E_GLPRT_BPTCL_BPTCL_SHIFT 0
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#define I40E_GLPRT_BPTCL_BPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPTCL_BPTCL_SHIFT)
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#define I40E_GLPRT_CRCERRS(_i) (0x00300080 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
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#define I40E_GLPRT_CRCERRS_MAX_INDEX 3
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#define I40E_GLPRT_CRCERRS_CRCERRS_SHIFT 0
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@ -2620,10 +2627,6 @@
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#define I40E_GLPRT_TDOLD_MAX_INDEX 3
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#define I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT 0
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#define I40E_GLPRT_TDOLD_GLPRT_TDOLD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT)
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#define I40E_GLPRT_TDPC(_i) (0x00375400 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
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#define I40E_GLPRT_TDPC_MAX_INDEX 3
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#define I40E_GLPRT_TDPC_TDPC_SHIFT 0
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#define I40E_GLPRT_TDPC_TDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_TDPC_TDPC_SHIFT)
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#define I40E_GLPRT_UPRCH(_i) (0x003005A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
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#define I40E_GLPRT_UPRCH_MAX_INDEX 3
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#define I40E_GLPRT_UPRCH_UPRCH_SHIFT 0
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@ -2990,9 +2993,6 @@
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#define I40E_PRTTSYN_TXTIME_L 0x001E41C0 /* Reset: GLOBR */
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#define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT 0
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#define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT)
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#define I40E_GLSCD_QUANTA 0x000B2080 /* Reset: CORER */
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#define I40E_GLSCD_QUANTA_TSCDQUANTA_SHIFT 0
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#define I40E_GLSCD_QUANTA_TSCDQUANTA_MASK I40E_MASK(0x7, I40E_GLSCD_QUANTA_TSCDQUANTA_SHIFT)
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#define I40E_GL_MDET_RX 0x0012A510 /* Reset: CORER */
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#define I40E_GL_MDET_RX_FUNCTION_SHIFT 0
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#define I40E_GL_MDET_RX_FUNCTION_MASK I40E_MASK(0xFF, I40E_GL_MDET_RX_FUNCTION_SHIFT)
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#define I40E_VFINT_ITRN1_MAX_INDEX 2
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#define I40E_VFINT_ITRN1_INTERVAL_SHIFT 0
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#define I40E_VFINT_ITRN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN1_INTERVAL_SHIFT)
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#define I40E_VFINT_STAT_CTL01 0x00005400 /* Reset: VFR */
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#define I40E_VFINT_STAT_CTL01 0x00005400 /* Reset: CORER */
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#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2
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#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT)
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#define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */
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#define I40E_PRTDCB_RUP2TC_UP6TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP6TC_SHIFT)
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#define I40E_PRTDCB_RUP2TC_UP7TC_SHIFT 21
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#define I40E_PRTDCB_RUP2TC_UP7TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP7TC_SHIFT)
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#define I40E_PRTDCB_RUPTQ(_i) (0x00122400 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
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#define I40E_PRTDCB_RUPTQ_MAX_INDEX 7
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#define I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT 0
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#define I40E_PRTDCB_RUPTQ_RXQNUM_MASK I40E_MASK(0x3FFF, I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT)
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#define I40E_PRTDCB_TC2PFC 0x001C0980 /* Reset: CORER */
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#define I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT 0
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#define I40E_PRTDCB_TC2PFC_TC2PFC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT)
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#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT)
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#define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT 20
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#define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_MASK I40E_MASK(0x3F, I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT)
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#define I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_SHIFT 26
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#define I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_MASK I40E_MASK(0xF, I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_SHIFT)
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#define I40E_GLGEN_GPIO_SET 0x00088184 /* Reset: POR */
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#define I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT 0
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#define I40E_GLGEN_GPIO_SET_GPIO_INDX_MASK I40E_MASK(0x1F, I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT)
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#define I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT 17
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#define I40E_GLGEN_MDIO_CTRL_CONTMDC_MASK I40E_MASK(0x1, I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT)
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#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT 18
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#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_MASK I40E_MASK(0x3FFF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT)
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#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_MASK I40E_MASK(0x7FF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT)
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#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_SHIFT 29
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#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_MASK I40E_MASK(0x7, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_SHIFT)
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||||
#define I40E_GLGEN_MDIO_I2C_SEL(_i) (0x000881C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
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||||
#define I40E_GLGEN_MDIO_I2C_SEL_MAX_INDEX 3
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||||
#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT 0
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||||
|
|
@ -548,9 +556,6 @@
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|||
#define I40E_GLGEN_RSTCTL_GRSTDEL_MASK I40E_MASK(0x3F, I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT)
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||||
#define I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT 8
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||||
#define I40E_GLGEN_RSTCTL_ECC_RST_ENA_MASK I40E_MASK(0x1, I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT)
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||||
#define I40E_GLGEN_RSTENA_EMP 0x000B818C /* Reset: POR */
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||||
#define I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_SHIFT 0
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||||
#define I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK I40E_MASK(0x1, I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_SHIFT)
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||||
#define I40E_GLGEN_RTRIG 0x000B8190 /* Reset: CORER */
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||||
#define I40E_GLGEN_RTRIG_CORER_SHIFT 0
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#define I40E_GLGEN_RTRIG_CORER_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_CORER_SHIFT)
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||||
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@ -1066,7 +1071,7 @@
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#define I40E_PFINT_RATEN_INTERVAL_MASK I40E_MASK(0x3F, I40E_PFINT_RATEN_INTERVAL_SHIFT)
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||||
#define I40E_PFINT_RATEN_INTRL_ENA_SHIFT 6
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||||
#define I40E_PFINT_RATEN_INTRL_ENA_MASK I40E_MASK(0x1, I40E_PFINT_RATEN_INTRL_ENA_SHIFT)
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||||
#define I40E_PFINT_STAT_CTL0 0x00038400 /* Reset: PFR */
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||||
#define I40E_PFINT_STAT_CTL0 0x00038400 /* Reset: CORER */
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||||
#define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2
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||||
#define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT)
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||||
#define I40E_QINT_RQCTL(_Q) (0x0003A000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
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||||
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@ -1171,7 +1176,7 @@
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#define I40E_VFINT_ITRN_MAX_INDEX 2
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||||
#define I40E_VFINT_ITRN_INTERVAL_SHIFT 0
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#define I40E_VFINT_ITRN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN_INTERVAL_SHIFT)
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||||
#define I40E_VFINT_STAT_CTL0(_VF) (0x0002A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
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||||
#define I40E_VFINT_STAT_CTL0(_VF) (0x0002A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
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||||
#define I40E_VFINT_STAT_CTL0_MAX_INDEX 127
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||||
#define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2
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||||
#define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT)
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||||
|
|
@ -1803,9 +1808,6 @@
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|||
#define I40E_GLPCI_GSCN_0_3_MAX_INDEX 3
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||||
#define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT 0
|
||||
#define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT)
|
||||
#define I40E_GLPCI_LATCT 0x0009C4B4 /* Reset: PCIR */
|
||||
#define I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_SHIFT 0
|
||||
#define I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_SHIFT)
|
||||
#define I40E_GLPCI_LBARCTRL 0x000BE484 /* Reset: POR */
|
||||
#define I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT 0
|
||||
#define I40E_GLPCI_LBARCTRL_PREFBAR_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT)
|
||||
|
|
@ -1902,6 +1904,11 @@
|
|||
#define I40E_GLPCI_VFSUP_VF_PREFETCH_MASK I40E_MASK(0x1, I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT)
|
||||
#define I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT 1
|
||||
#define I40E_GLPCI_VFSUP_VR_BAR_TYPE_MASK I40E_MASK(0x1, I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT)
|
||||
#define I40E_GLTPH_CTRL 0x000BE480 /* Reset: PCIR */
|
||||
#define I40E_GLTPH_CTRL_DESC_PH_SHIFT 9
|
||||
#define I40E_GLTPH_CTRL_DESC_PH_MASK I40E_MASK(0x3, I40E_GLTPH_CTRL_DESC_PH_SHIFT)
|
||||
#define I40E_GLTPH_CTRL_DATA_PH_SHIFT 11
|
||||
#define I40E_GLTPH_CTRL_DATA_PH_MASK I40E_MASK(0x3, I40E_GLTPH_CTRL_DATA_PH_SHIFT)
|
||||
#define I40E_PF_FUNC_RID 0x0009C000 /* Reset: PCIR */
|
||||
#define I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT 0
|
||||
#define I40E_PF_FUNC_RID_FUNCTION_NUMBER_MASK I40E_MASK(0x7, I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT)
|
||||
|
|
@ -2374,20 +2381,20 @@
|
|||
#define I40E_GL_RXERR2_L_FCOEDIXAC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR2_L_FCOEDIXAC_SHIFT)
|
||||
#define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
|
||||
#define I40E_GLPRT_BPRCH_MAX_INDEX 3
|
||||
#define I40E_GLPRT_BPRCH_UPRCH_SHIFT 0
|
||||
#define I40E_GLPRT_BPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPRCH_UPRCH_SHIFT)
|
||||
#define I40E_GLPRT_BPRCH_BPRCH_SHIFT 0
|
||||
#define I40E_GLPRT_BPRCH_BPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPRCH_BPRCH_SHIFT)
|
||||
#define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
|
||||
#define I40E_GLPRT_BPRCL_MAX_INDEX 3
|
||||
#define I40E_GLPRT_BPRCL_UPRCH_SHIFT 0
|
||||
#define I40E_GLPRT_BPRCL_UPRCH_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPRCL_UPRCH_SHIFT)
|
||||
#define I40E_GLPRT_BPRCL_BPRCL_SHIFT 0
|
||||
#define I40E_GLPRT_BPRCL_BPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPRCL_BPRCL_SHIFT)
|
||||
#define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
|
||||
#define I40E_GLPRT_BPTCH_MAX_INDEX 3
|
||||
#define I40E_GLPRT_BPTCH_UPRCH_SHIFT 0
|
||||
#define I40E_GLPRT_BPTCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPTCH_UPRCH_SHIFT)
|
||||
#define I40E_GLPRT_BPTCH_BPTCH_SHIFT 0
|
||||
#define I40E_GLPRT_BPTCH_BPTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPTCH_BPTCH_SHIFT)
|
||||
#define I40E_GLPRT_BPTCL(_i) (0x00300A00 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
|
||||
#define I40E_GLPRT_BPTCL_MAX_INDEX 3
|
||||
#define I40E_GLPRT_BPTCL_UPRCH_SHIFT 0
|
||||
#define I40E_GLPRT_BPTCL_UPRCH_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPTCL_UPRCH_SHIFT)
|
||||
#define I40E_GLPRT_BPTCL_BPTCL_SHIFT 0
|
||||
#define I40E_GLPRT_BPTCL_BPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPTCL_BPTCL_SHIFT)
|
||||
#define I40E_GLPRT_CRCERRS(_i) (0x00300080 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
|
||||
#define I40E_GLPRT_CRCERRS_MAX_INDEX 3
|
||||
#define I40E_GLPRT_CRCERRS_CRCERRS_SHIFT 0
|
||||
|
|
@ -2620,10 +2627,6 @@
|
|||
#define I40E_GLPRT_TDOLD_MAX_INDEX 3
|
||||
#define I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT 0
|
||||
#define I40E_GLPRT_TDOLD_GLPRT_TDOLD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT)
|
||||
#define I40E_GLPRT_TDPC(_i) (0x00375400 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
|
||||
#define I40E_GLPRT_TDPC_MAX_INDEX 3
|
||||
#define I40E_GLPRT_TDPC_TDPC_SHIFT 0
|
||||
#define I40E_GLPRT_TDPC_TDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_TDPC_TDPC_SHIFT)
|
||||
#define I40E_GLPRT_UPRCH(_i) (0x003005A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
|
||||
#define I40E_GLPRT_UPRCH_MAX_INDEX 3
|
||||
#define I40E_GLPRT_UPRCH_UPRCH_SHIFT 0
|
||||
|
|
@ -2990,9 +2993,6 @@
|
|||
#define I40E_PRTTSYN_TXTIME_L 0x001E41C0 /* Reset: GLOBR */
|
||||
#define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT 0
|
||||
#define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT)
|
||||
#define I40E_GLSCD_QUANTA 0x000B2080 /* Reset: CORER */
|
||||
#define I40E_GLSCD_QUANTA_TSCDQUANTA_SHIFT 0
|
||||
#define I40E_GLSCD_QUANTA_TSCDQUANTA_MASK I40E_MASK(0x7, I40E_GLSCD_QUANTA_TSCDQUANTA_SHIFT)
|
||||
#define I40E_GL_MDET_RX 0x0012A510 /* Reset: CORER */
|
||||
#define I40E_GL_MDET_RX_FUNCTION_SHIFT 0
|
||||
#define I40E_GL_MDET_RX_FUNCTION_MASK I40E_MASK(0xFF, I40E_GL_MDET_RX_FUNCTION_SHIFT)
|
||||
|
|
@ -3258,7 +3258,7 @@
|
|||
#define I40E_VFINT_ITRN1_MAX_INDEX 2
|
||||
#define I40E_VFINT_ITRN1_INTERVAL_SHIFT 0
|
||||
#define I40E_VFINT_ITRN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN1_INTERVAL_SHIFT)
|
||||
#define I40E_VFINT_STAT_CTL01 0x00005400 /* Reset: VFR */
|
||||
#define I40E_VFINT_STAT_CTL01 0x00005400 /* Reset: CORER */
|
||||
#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2
|
||||
#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT)
|
||||
#define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */
|
||||
|
|
|
|||
Loading…
Reference in New Issue