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drm/nouveau/core: fix the assumption that NVDEV_XXXX is always under 32 

It fixes a bug that would have been introduced when adding more
sudevs/engines.

Signed-off-by: Martin Peres <martin.peres@labri.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Martin Peres 2012-11-27 00:30:32 +01:00 committed by Ben Skeggs
parent d1be7e9be1
commit 507ceb1518
11 changed files with 58 additions and 58 deletions
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2
drivers/gpu/drm/nouveau/core/engine/fifo/base.c
View File

@ -34,7 +34,7 @@ nouveau_fifo_channel_create_(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass,
int bar, u32 addr, u32 size, u32 pushbuf,
u32 engmask, int len, void **ptr)
u64 engmask, int len, void **ptr)
{
struct nouveau_device *device = nv_device(engine);
struct nouveau_fifo *priv = (void *)engine;

6
drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
View File

@ -126,9 +126,9 @@ nv04_fifo_chan_ctor(struct nouveau_object *parent,
ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000,
0x10000, args->pushbuf,
(1 << NVDEV_ENGINE_DMAOBJ) |
(1 << NVDEV_ENGINE_SW) |
(1 << NVDEV_ENGINE_GR), &chan);
(1ULL << NVDEV_ENGINE_DMAOBJ) |
(1ULL << NVDEV_ENGINE_SW) |
(1ULL << NVDEV_ENGINE_GR), &chan);
*pobject = nv_object(chan);
if (ret)
return ret;

6
drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c
View File

@ -69,9 +69,9 @@ nv10_fifo_chan_ctor(struct nouveau_object *parent,
ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000,
0x10000, args->pushbuf,
(1 << NVDEV_ENGINE_DMAOBJ) |
(1 << NVDEV_ENGINE_SW) |
(1 << NVDEV_ENGINE_GR), &chan);
(1ULL << NVDEV_ENGINE_DMAOBJ) |
(1ULL << NVDEV_ENGINE_SW) |
(1ULL << NVDEV_ENGINE_GR), &chan);
*pobject = nv_object(chan);
if (ret)
return ret;

8
drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c
View File

@ -74,10 +74,10 @@ nv17_fifo_chan_ctor(struct nouveau_object *parent,
ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000,
0x10000, args->pushbuf,
(1 << NVDEV_ENGINE_DMAOBJ) |
(1 << NVDEV_ENGINE_SW) |
(1 << NVDEV_ENGINE_GR) |
(1 << NVDEV_ENGINE_MPEG), /* NV31- */
(1ULL << NVDEV_ENGINE_DMAOBJ) |
(1ULL << NVDEV_ENGINE_SW) |
(1ULL << NVDEV_ENGINE_GR) |
(1ULL << NVDEV_ENGINE_MPEG), /* NV31- */
&chan);
*pobject = nv_object(chan);
if (ret)

8
drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
View File

@ -192,10 +192,10 @@ nv40_fifo_chan_ctor(struct nouveau_object *parent,
ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
0x1000, args->pushbuf,
(1 << NVDEV_ENGINE_DMAOBJ) |
(1 << NVDEV_ENGINE_SW) |
(1 << NVDEV_ENGINE_GR) |
(1 << NVDEV_ENGINE_MPEG), &chan);
(1ULL << NVDEV_ENGINE_DMAOBJ) |
(1ULL << NVDEV_ENGINE_SW) |
(1ULL << NVDEV_ENGINE_GR) |
(1ULL << NVDEV_ENGINE_MPEG), &chan);
*pobject = nv_object(chan);
if (ret)
return ret;

16
drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
View File

@ -194,10 +194,10 @@ nv50_fifo_chan_ctor_dma(struct nouveau_object *parent,
ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
0x2000, args->pushbuf,
(1 << NVDEV_ENGINE_DMAOBJ) |
(1 << NVDEV_ENGINE_SW) |
(1 << NVDEV_ENGINE_GR) |
(1 << NVDEV_ENGINE_MPEG), &chan);
(1ULL << NVDEV_ENGINE_DMAOBJ) |
(1ULL << NVDEV_ENGINE_SW) |
(1ULL << NVDEV_ENGINE_GR) |
(1ULL << NVDEV_ENGINE_MPEG), &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@ -247,10 +247,10 @@ nv50_fifo_chan_ctor_ind(struct nouveau_object *parent,
ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
0x2000, args->pushbuf,
(1 << NVDEV_ENGINE_DMAOBJ) |
(1 << NVDEV_ENGINE_SW) |
(1 << NVDEV_ENGINE_GR) |
(1 << NVDEV_ENGINE_MPEG), &chan);
(1ULL << NVDEV_ENGINE_DMAOBJ) |
(1ULL << NVDEV_ENGINE_SW) |
(1ULL << NVDEV_ENGINE_GR) |
(1ULL << NVDEV_ENGINE_MPEG), &chan);
*pobject = nv_object(chan);
if (ret)
return ret;

44
drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
View File

@ -163,17 +163,17 @@ nv84_fifo_chan_ctor_dma(struct nouveau_object *parent,
ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
0x2000, args->pushbuf,
(1 << NVDEV_ENGINE_DMAOBJ) |
(1 << NVDEV_ENGINE_SW) |
(1 << NVDEV_ENGINE_GR) |
(1 << NVDEV_ENGINE_MPEG) |
(1 << NVDEV_ENGINE_ME) |
(1 << NVDEV_ENGINE_VP) |
(1 << NVDEV_ENGINE_CRYPT) |
(1 << NVDEV_ENGINE_BSP) |
(1 << NVDEV_ENGINE_PPP) |
(1 << NVDEV_ENGINE_COPY0) |
(1 << NVDEV_ENGINE_UNK1C1), &chan);
(1ULL << NVDEV_ENGINE_DMAOBJ) |
(1ULL << NVDEV_ENGINE_SW) |
(1ULL << NVDEV_ENGINE_GR) |
(1ULL << NVDEV_ENGINE_MPEG) |
(1ULL << NVDEV_ENGINE_ME) |
(1ULL << NVDEV_ENGINE_VP) |
(1ULL << NVDEV_ENGINE_CRYPT) |
(1ULL << NVDEV_ENGINE_BSP) |
(1ULL << NVDEV_ENGINE_PPP) |
(1ULL << NVDEV_ENGINE_COPY0) |
(1ULL << NVDEV_ENGINE_UNK1C1), &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@ -225,17 +225,17 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent,
ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
0x2000, args->pushbuf,
(1 << NVDEV_ENGINE_DMAOBJ) |
(1 << NVDEV_ENGINE_SW) |
(1 << NVDEV_ENGINE_GR) |
(1 << NVDEV_ENGINE_MPEG) |
(1 << NVDEV_ENGINE_ME) |
(1 << NVDEV_ENGINE_VP) |
(1 << NVDEV_ENGINE_CRYPT) |
(1 << NVDEV_ENGINE_BSP) |
(1 << NVDEV_ENGINE_PPP) |
(1 << NVDEV_ENGINE_COPY0) |
(1 << NVDEV_ENGINE_UNK1C1), &chan);
(1ULL << NVDEV_ENGINE_DMAOBJ) |
(1ULL << NVDEV_ENGINE_SW) |
(1ULL << NVDEV_ENGINE_GR) |
(1ULL << NVDEV_ENGINE_MPEG) |
(1ULL << NVDEV_ENGINE_ME) |
(1ULL << NVDEV_ENGINE_VP) |
(1ULL << NVDEV_ENGINE_CRYPT) |
(1ULL << NVDEV_ENGINE_BSP) |
(1ULL << NVDEV_ENGINE_PPP) |
(1ULL << NVDEV_ENGINE_COPY0) |
(1ULL << NVDEV_ENGINE_UNK1C1), &chan);
*pobject = nv_object(chan);
if (ret)
return ret;

14
drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
View File

@ -181,13 +181,13 @@ nvc0_fifo_chan_ctor(struct nouveau_object *parent,
ret = nouveau_fifo_channel_create(parent, engine, oclass, 1,
priv->user.bar.offset, 0x1000,
args->pushbuf,
(1 << NVDEV_ENGINE_SW) |
(1 << NVDEV_ENGINE_GR) |
(1 << NVDEV_ENGINE_COPY0) |
(1 << NVDEV_ENGINE_COPY1) |
(1 << NVDEV_ENGINE_BSP) |
(1 << NVDEV_ENGINE_VP) |
(1 << NVDEV_ENGINE_PPP), &chan);
(1ULL << NVDEV_ENGINE_SW) |
(1ULL << NVDEV_ENGINE_GR) |
(1ULL << NVDEV_ENGINE_COPY0) |
(1ULL << NVDEV_ENGINE_COPY1) |
(1ULL << NVDEV_ENGINE_BSP) |
(1ULL << NVDEV_ENGINE_VP) |
(1ULL << NVDEV_ENGINE_PPP), &chan);
*pobject = nv_object(chan);
if (ret)
return ret;

8
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
View File

@ -38,12 +38,12 @@
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#define _(a,b) { (a), ((1 << (a)) | (b)) }
#define _(a,b) { (a), ((1ULL << (a)) | (b)) }
static const struct {
int subdev;
u32 mask;
u64 subdev;
u64 mask;
} fifo_engine[] = {
_(NVDEV_ENGINE_GR , (1 << NVDEV_ENGINE_SW)),
_(NVDEV_ENGINE_GR , (1ULL << NVDEV_ENGINE_SW)),
_(NVDEV_ENGINE_VP , 0),
_(NVDEV_ENGINE_PPP , 0),
_(NVDEV_ENGINE_BSP , 0),

2
drivers/gpu/drm/nouveau/core/include/core/parent.h
View File

@ -14,7 +14,7 @@ struct nouveau_parent {
struct nouveau_object base;
struct nouveau_sclass *sclass;
u32 engine;
u64 engine;
int (*context_attach)(struct nouveau_object *,
struct nouveau_object *);

2
drivers/gpu/drm/nouveau/core/include/engine/fifo.h
View File

@ -33,7 +33,7 @@ int nouveau_fifo_channel_create_(struct nouveau_object *,
struct nouveau_object *,
struct nouveau_oclass *,
int bar, u32 addr, u32 size, u32 push,
u32 engmask, int len, void **);
u64 engmask, int len, void **);
void nouveau_fifo_channel_destroy(struct nouveau_fifo_chan *);
#define _nouveau_fifo_channel_init _nouveau_namedb_init