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powerpc/64s/hash: avoid the POWER5 < DD2.1 slb invalidate workaround on POWER8/9 

I only have POWER8/9 to test, so just remove it for those.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Nicholas Piggin 2018-09-15 01:30:46 +10:00 committed by Michael Ellerman
parent 09b4438db1
commit 505ea82eab
2 changed files with 7 additions and 3 deletions
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2
arch/powerpc/kernel/entry_64.S
View File

@ -672,7 +672,9 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
isync
slbie r6
BEGIN_FTR_SECTION
slbie r6 /* Workaround POWER5 < DD2.1 issue */
END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
slbmte r7,r0
isync
2:

8
arch/powerpc/mm/slb.c
View File

@ -326,9 +326,11 @@ void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
__slb_flush_and_rebolt();
}
/* Workaround POWER5 < DD2.1 issue */
if (offset == 1 || offset > SLB_CACHE_ENTRIES)
asm volatile("slbie %0" : : "r" (slbie_data));
if (!cpu_has_feature(CPU_FTR_ARCH_207S)) {
/* Workaround POWER5 < DD2.1 issue */
if (offset == 1 || offset > SLB_CACHE_ENTRIES)
asm volatile("slbie %0" : : "r" (slbie_data));
}
get_paca()->slb_cache_ptr = 0;
copy_mm_to_paca(mm);