x86/cpu: Unify cpu_init()
Similar to copy_thread_tls() the 32bit and 64bit implementations of cpu_init() are very similar and unification avoids duplicate changes in the future. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Andy Lutomirski <luto@kernel.org>
This commit is contained in:
Thomas Gleixner
parent
2fff071d28
commit
505b789996
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@ -53,10 +53,7 @@
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#include <asm/microcode_intel.h>
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#include <asm/intel-family.h>
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#include <asm/cpu_device_id.h>
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#ifdef CONFIG_X86_LOCAL_APIC
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#include <asm/uv/uv.h>
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#endif
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#include "cpu.h"
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@ -1749,7 +1746,7 @@ static void wait_for_master_cpu(int cpu)
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}
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#ifdef CONFIG_X86_64
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static void setup_getcpu(int cpu)
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static inline void setup_getcpu(int cpu)
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{
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unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu));
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struct desc_struct d = { };
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@ -1769,7 +1766,43 @@ static void setup_getcpu(int cpu)
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write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S);
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}
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static inline void ucode_cpu_init(int cpu)
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{
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if (cpu)
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load_ucode_ap();
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}
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static inline void tss_setup_ist(struct tss_struct *tss)
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{
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/* Set up the per-CPU TSS IST stacks */
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tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF);
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tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI);
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tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB);
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tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE);
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}
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static inline void gdt_setup_doublefault_tss(int cpu) { }
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#else /* CONFIG_X86_64 */
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static inline void setup_getcpu(int cpu) { }
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static inline void ucode_cpu_init(int cpu)
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{
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show_ucode_info_early();
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}
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static inline void tss_setup_ist(struct tss_struct *tss) { }
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static inline void gdt_setup_doublefault_tss(int cpu)
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{
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#ifdef CONFIG_DOUBLEFAULT
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/* Set up the doublefault TSS pointer in the GDT */
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__set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
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#endif
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}
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#endif /* !CONFIG_X86_64 */
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/*
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* cpu_init() initializes state that is per-CPU. Some data is already
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@ -1777,21 +1810,15 @@ static void setup_getcpu(int cpu)
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* and IDT. We reload them nevertheless, this function acts as a
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* 'CPU state barrier', nothing should get across.
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*/
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#ifdef CONFIG_X86_64
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void cpu_init(void)
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{
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struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
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struct task_struct *cur = current;
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int cpu = raw_smp_processor_id();
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struct task_struct *me;
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struct tss_struct *t;
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int i;
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wait_for_master_cpu(cpu);
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if (cpu)
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load_ucode_ap();
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t = &per_cpu(cpu_tss_rw, cpu);
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ucode_cpu_init(cpu);
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#ifdef CONFIG_NUMA
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if (this_cpu_read(numa_node) == 0 &&
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@ -1800,63 +1827,48 @@ void cpu_init(void)
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#endif
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setup_getcpu(cpu);
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me = current;
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pr_debug("Initializing CPU#%d\n", cpu);
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if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) ||
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boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE))
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cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
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/*
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* Initialize the per-CPU GDT with the boot GDT,
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* and set up the GDT descriptor:
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*/
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switch_to_new_gdt(cpu);
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loadsegment(fs, 0);
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load_current_idt();
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memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
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if (IS_ENABLED(CONFIG_X86_64)) {
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loadsegment(fs, 0);
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memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
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syscall_init();
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wrmsrl(MSR_FS_BASE, 0);
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wrmsrl(MSR_KERNEL_GS_BASE, 0);
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barrier();
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x86_configure_nx();
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x2apic_setup();
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/*
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* set up and load the per-CPU TSS
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*/
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if (!t->x86_tss.ist[0]) {
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t->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF);
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t->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI);
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t->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB);
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t->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE);
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}
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t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;
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/*
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* <= is required because the CPU will access up to
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* 8 bits beyond the end of the IO permission bitmap.
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*/
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for (i = 0; i <= IO_BITMAP_LONGS; i++)
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t->io_bitmap[i] = ~0UL;
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mmgrab(&init_mm);
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me->active_mm = &init_mm;
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BUG_ON(me->mm);
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cur->active_mm = &init_mm;
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BUG_ON(cur->mm);
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initialize_tlbstate_and_flush();
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enter_lazy_tlb(&init_mm, me);
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enter_lazy_tlb(&init_mm, cur);
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/*
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* Initialize the TSS. sp0 points to the entry trampoline stack
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* regardless of what task is running.
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*/
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/* Initialize the TSS. */
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tss_setup_ist(tss);
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tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;
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memset(tss->io_bitmap, 0xff, sizeof(tss->io_bitmap));
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set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
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load_TR_desc();
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/*
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* sp0 points to the entry trampoline stack regardless of what task
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* is running.
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*/
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load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
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load_mm_ldt(&init_mm);
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@ -1864,6 +1876,8 @@ void cpu_init(void)
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clear_all_debug_regs();
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dbg_restore_debug_regs();
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gdt_setup_doublefault_tss(cpu);
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fpu__init_cpu();
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if (is_uv_system())
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@ -1872,63 +1886,6 @@ void cpu_init(void)
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load_fixmap_gdt(cpu);
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}
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#else
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void cpu_init(void)
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{
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int cpu = smp_processor_id();
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struct task_struct *curr = current;
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struct tss_struct *t = &per_cpu(cpu_tss_rw, cpu);
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wait_for_master_cpu(cpu);
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show_ucode_info_early();
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pr_info("Initializing CPU#%d\n", cpu);
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if (cpu_feature_enabled(X86_FEATURE_VME) ||
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boot_cpu_has(X86_FEATURE_TSC) ||
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boot_cpu_has(X86_FEATURE_DE))
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cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
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load_current_idt();
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switch_to_new_gdt(cpu);
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/*
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* Set up and load the per-CPU TSS and LDT
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*/
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mmgrab(&init_mm);
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curr->active_mm = &init_mm;
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BUG_ON(curr->mm);
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initialize_tlbstate_and_flush();
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enter_lazy_tlb(&init_mm, curr);
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/*
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* Initialize the TSS. sp0 points to the entry trampoline stack
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* regardless of what task is running.
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*/
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set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
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load_TR_desc();
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load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
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load_mm_ldt(&init_mm);
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t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;
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#ifdef CONFIG_DOUBLEFAULT
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/* Set up doublefault TSS pointer in the GDT */
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__set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
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#endif
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clear_all_debug_regs();
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dbg_restore_debug_regs();
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fpu__init_cpu();
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load_fixmap_gdt(cpu);
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}
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#endif
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/*
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* The microcode loader calls this upon late microcode load to recheck features,
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* only when microcode has been updated. Caller holds microcode_mutex and CPU
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