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clk: sunxi-ng: v3s: Fix incorrect number of hw_clks. 

The hws field of sun8i_v3s_hw_clks has only 74
members. However, the number specified by CLK_NUMBER
is 77 (= CLK_I2S0 + 1). This leads to runtime segmentation
fault that is not always reproducible.

This patch fixes the problem by specifying correct clock number.

Signed-off-by: Yunhao Tian <18373444@buaa.edu.cn>
[Maxime: Also remove the CLK_NUMBER definition]
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
This commit is contained in:
Yunhao Tian 2019-11-25 20:58:32 +08:00 committed by Maxime Ripard
parent e42617b825
commit 4ff40d140e
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GPG Key ID: E3EF0D6F671851C5
2 changed files with 2 additions and 4 deletions
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4
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
View File

@ -618,7 +618,7 @@ static struct clk_hw_onecell_data sun8i_v3s_hw_clks = {
[CLK_MBUS] = &mbus_clk.common.hw, [CLK_MBUS] = &mbus_clk.common.hw,
[CLK_MIPI_CSI] = &mipi_csi_clk.common.hw, [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw,
}, },
.num = CLK_NUMBER, .num = CLK_PLL_DDR1 + 1,
}; };
static struct clk_hw_onecell_data sun8i_v3_hw_clks = { static struct clk_hw_onecell_data sun8i_v3_hw_clks = {
@ -700,7 +700,7 @@ static struct clk_hw_onecell_data sun8i_v3_hw_clks = {
[CLK_MBUS] = &mbus_clk.common.hw, [CLK_MBUS] = &mbus_clk.common.hw,
[CLK_MIPI_CSI] = &mipi_csi_clk.common.hw, [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw,
}, },
.num = CLK_NUMBER, .num = CLK_I2S0 + 1,
}; };
static struct ccu_reset_map sun8i_v3s_ccu_resets[] = { static struct ccu_reset_map sun8i_v3s_ccu_resets[] = {

2
drivers/clk/sunxi-ng/ccu-sun8i-v3s.h
View File

@ -51,6 +51,4 @@
#define CLK_PLL_DDR1 74 #define CLK_PLL_DDR1 74
#define CLK_NUMBER (CLK_I2S0 + 1)
#endif /* _CCU_SUN8I_H3_H_ */ #endif /* _CCU_SUN8I_H3_H_ */