drm/amd/display: Start using the new pp_smu interface
[Why] PPLib has impelemented the new pp_smu interface [How] Use the new functions if available instead of the old interface 'set_display_requirement' and 'dcn1_pplib_apply_display_requirements'. Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by: Fatemeh Darbehani <Fatemeh.Darbehani@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Su Chung <Su.Chung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -161,58 +161,6 @@ static int get_active_display_cnt(
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return display_count;
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return display_count;
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}
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}
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static void notify_deep_sleep_dcfclk_to_smu(
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struct pp_smu_funcs_rv *pp_smu, int min_dcef_deep_sleep_clk_khz)
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{
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int min_dcef_deep_sleep_clk_mhz; //minimum required DCEF Deep Sleep clock in mhz
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/*
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* if function pointer not set up, this message is
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* sent as part of pplib_apply_display_requirements.
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* So just return.
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*/
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if (!pp_smu || !pp_smu->set_min_deep_sleep_dcfclk)
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return;
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min_dcef_deep_sleep_clk_mhz = (min_dcef_deep_sleep_clk_khz + 999) / 1000; //Round up
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pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, min_dcef_deep_sleep_clk_mhz);
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}
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static void notify_hard_min_dcfclk_to_smu(
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struct pp_smu_funcs_rv *pp_smu, int min_dcf_clk_khz)
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{
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int min_dcf_clk_mhz; //minimum required DCF clock in mhz
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/*
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* if function pointer not set up, this message is
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* sent as part of pplib_apply_display_requirements.
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* So just return.
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*/
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if (!pp_smu || !pp_smu->set_hard_min_dcfclk_by_freq)
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return;
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min_dcf_clk_mhz = min_dcf_clk_khz / 1000;
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pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, min_dcf_clk_mhz);
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}
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static void notify_hard_min_fclk_to_smu(
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struct pp_smu_funcs_rv *pp_smu, int min_f_clk_khz)
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{
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int min_f_clk_mhz; //minimum required F clock in mhz
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/*
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* if function pointer not set up, this message is
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* sent as part of pplib_apply_display_requirements.
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* So just return.
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*/
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if (!pp_smu || !pp_smu->set_hard_min_fclk_by_freq)
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return;
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min_f_clk_mhz = min_f_clk_khz / 1000;
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pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, min_f_clk_mhz);
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}
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static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
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static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
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struct dc_state *context,
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struct dc_state *context,
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bool safe_to_lower)
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bool safe_to_lower)
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@ -224,7 +172,6 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
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&dc->res_pool->pp_smu_req;
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&dc->res_pool->pp_smu_req;
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struct pp_smu_display_requirement_rv smu_req = *smu_req_cur;
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struct pp_smu_display_requirement_rv smu_req = *smu_req_cur;
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struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;
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struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;
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uint32_t requested_dcf_clock_in_khz = 0;
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bool send_request_to_increase = false;
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bool send_request_to_increase = false;
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bool send_request_to_lower = false;
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bool send_request_to_lower = false;
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int display_count;
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int display_count;
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@ -244,9 +191,8 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
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*/
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*/
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if (pp_smu->set_display_count)
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if (pp_smu->set_display_count)
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pp_smu->set_display_count(&pp_smu->pp_smu, display_count);
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pp_smu->set_display_count(&pp_smu->pp_smu, display_count);
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else
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smu_req.display_count = display_count;
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smu_req.display_count = display_count;
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}
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}
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if (new_clocks->dispclk_khz > clk_mgr->clks.dispclk_khz
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if (new_clocks->dispclk_khz > clk_mgr->clks.dispclk_khz
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@ -269,8 +215,6 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
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clk_mgr->clks.fclk_khz = new_clocks->fclk_khz;
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clk_mgr->clks.fclk_khz = new_clocks->fclk_khz;
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smu_req.hard_min_fclk_mhz = new_clocks->fclk_khz / 1000;
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smu_req.hard_min_fclk_mhz = new_clocks->fclk_khz / 1000;
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notify_hard_min_fclk_to_smu(pp_smu, new_clocks->fclk_khz);
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send_request_to_lower = true;
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send_request_to_lower = true;
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}
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}
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@ -285,7 +229,7 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
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if (should_set_clock(safe_to_lower,
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if (should_set_clock(safe_to_lower,
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new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) {
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new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) {
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clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
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clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
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smu_req.min_deep_sleep_dcefclk_mhz = new_clocks->dcfclk_deep_sleep_khz / 1000;
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smu_req.min_deep_sleep_dcefclk_mhz = (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000;
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send_request_to_lower = true;
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send_request_to_lower = true;
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}
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}
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@ -295,15 +239,18 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
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*/
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*/
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if (send_request_to_increase) {
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if (send_request_to_increase) {
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/*use dcfclk to request voltage*/
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/*use dcfclk to request voltage*/
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requested_dcf_clock_in_khz = dcn_find_dcfclk_suits_all(dc, new_clocks);
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if (pp_smu->set_hard_min_fclk_by_freq &&
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pp_smu->set_hard_min_dcfclk_by_freq &&
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pp_smu->set_min_deep_sleep_dcfclk) {
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notify_hard_min_dcfclk_to_smu(pp_smu, requested_dcf_clock_in_khz);
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pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, smu_req.hard_min_fclk_mhz);
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pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, smu_req.hard_min_dcefclk_mhz);
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if (pp_smu->set_display_requirement)
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pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, smu_req.min_deep_sleep_dcefclk_mhz);
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pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
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} else {
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if (pp_smu->set_display_requirement)
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notify_deep_sleep_dcfclk_to_smu(pp_smu, clk_mgr->clks.dcfclk_deep_sleep_khz);
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pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
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dcn1_pplib_apply_display_requirements(dc, context);
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dcn1_pplib_apply_display_requirements(dc, context);
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}
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}
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}
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/* dcn1 dppclk is tied to dispclk */
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/* dcn1 dppclk is tied to dispclk */
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@ -318,18 +265,20 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
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if (!send_request_to_increase && send_request_to_lower) {
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if (!send_request_to_increase && send_request_to_lower) {
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/*use dcfclk to request voltage*/
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/*use dcfclk to request voltage*/
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requested_dcf_clock_in_khz = dcn_find_dcfclk_suits_all(dc, new_clocks);
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if (pp_smu->set_hard_min_fclk_by_freq &&
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pp_smu->set_hard_min_dcfclk_by_freq &&
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pp_smu->set_min_deep_sleep_dcfclk) {
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notify_hard_min_dcfclk_to_smu(pp_smu, requested_dcf_clock_in_khz);
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pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, smu_req.hard_min_fclk_mhz);
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pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, smu_req.hard_min_dcefclk_mhz);
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if (pp_smu->set_display_requirement)
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pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, smu_req.min_deep_sleep_dcefclk_mhz);
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pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
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} else {
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if (pp_smu->set_display_requirement)
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notify_deep_sleep_dcfclk_to_smu(pp_smu, clk_mgr->clks.dcfclk_deep_sleep_khz);
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pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
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dcn1_pplib_apply_display_requirements(dc, context);
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dcn1_pplib_apply_display_requirements(dc, context);
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}
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}
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}
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*smu_req_cur = smu_req;
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*smu_req_cur = smu_req;
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}
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}
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static const struct clk_mgr_funcs dcn1_funcs = {
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static const struct clk_mgr_funcs dcn1_funcs = {
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