powerpc: Remove legacy iSeries bits from assembly files
This removes the various bits of assembly in the kernel entry, exception handling and SLB management code that were specific to running under the legacy iSeries hypervisor which is no longer supported. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt
parent
b078766026
commit
4f8cf36f48
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@ -272,26 +272,11 @@ label##_hv: \
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_MASKABLE_EXCEPTION_PSERIES(vec, label, \
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EXC_HV, SOFTEN_TEST_HV)
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#ifdef CONFIG_PPC_ISERIES
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#define DISABLE_INTS \
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li r11,0; \
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stb r11,PACASOFTIRQEN(r13); \
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BEGIN_FW_FTR_SECTION; \
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stb r11,PACAHARDIRQEN(r13); \
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END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES); \
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TRACE_DISABLE_INTS; \
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BEGIN_FW_FTR_SECTION; \
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mfmsr r10; \
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ori r10,r10,MSR_EE; \
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mtmsrd r10,1; \
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END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
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#else
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#define DISABLE_INTS \
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li r11,0; \
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stb r11,PACASOFTIRQEN(r13); \
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stb r11,PACAHARDIRQEN(r13); \
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TRACE_DISABLE_INTS
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#endif /* CONFIG_PPC_ISERIES */
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#define ENABLE_INTS \
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ld r12,_MSR(r1); \
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@ -127,17 +127,6 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
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stb r10,PACASOFTIRQEN(r13)
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stb r10,PACAHARDIRQEN(r13)
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std r10,SOFTE(r1)
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#ifdef CONFIG_PPC_ISERIES
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BEGIN_FW_FTR_SECTION
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/* Hack for handling interrupts when soft-enabling on iSeries */
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cmpdi cr1,r0,0x5555 /* syscall 0x5555 */
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andi. r10,r12,MSR_PR /* from kernel */
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crand 4*cr0+eq,4*cr1+eq,4*cr0+eq
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bne 2f
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b hardware_interrupt_entry
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2:
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END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
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#endif /* CONFIG_PPC_ISERIES */
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/* Hard enable interrupts */
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#ifdef CONFIG_PPC_BOOK3E
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@ -591,15 +580,10 @@ _GLOBAL(ret_from_except_lite)
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ld r4,TI_FLAGS(r9)
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andi. r0,r4,_TIF_USER_WORK_MASK
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bne do_work
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#endif
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#endif /* !CONFIG_PREEMPT */
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restore:
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BEGIN_FW_FTR_SECTION
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ld r5,SOFTE(r1)
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FW_FTR_SECTION_ELSE
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b .Liseries_check_pending_irqs
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ALT_FW_FTR_SECTION_END_IFCLR(FW_FEATURE_ISERIES)
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2:
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TRACE_AND_RESTORE_IRQ(r5);
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/* extract EE bit and use it to restore paca->hard_enabled */
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@ -669,30 +653,6 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
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#endif /* CONFIG_PPC_BOOK3E */
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.Liseries_check_pending_irqs:
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#ifdef CONFIG_PPC_ISERIES
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ld r5,SOFTE(r1)
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cmpdi 0,r5,0
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beq 2b
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/* Check for pending interrupts (iSeries) */
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ld r3,PACALPPACAPTR(r13)
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ld r3,LPPACAANYINT(r3)
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cmpdi r3,0
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beq+ 2b /* skip do_IRQ if no interrupts */
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li r3,0
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stb r3,PACASOFTIRQEN(r13) /* ensure we are soft-disabled */
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#ifdef CONFIG_TRACE_IRQFLAGS
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bl .trace_hardirqs_off
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mfmsr r10
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#endif
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ori r10,r10,MSR_EE
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mtmsrd r10 /* hard-enable again */
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl .do_IRQ
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b .ret_from_except_lite /* loop back and handle more */
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#endif
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do_work:
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#ifdef CONFIG_PREEMPT
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andi. r0,r3,MSR_PR /* Returning to user mode? */
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@ -19,7 +19,7 @@
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* We layout physical memory as follows:
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* 0x0000 - 0x00ff : Secondary processor spin code
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* 0x0100 - 0x2fff : pSeries Interrupt prologs
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* 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
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* 0x3000 - 0x5fff : interrupt support common interrupt prologs
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* 0x6000 - 0x6fff : Initial (CPU0) segment table
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* 0x7000 - 0x7fff : FWNMI data area
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* 0x8000 - : Early init and support code
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@ -458,6 +458,7 @@ machine_check_common:
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bl .machine_check_exception
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b .ret_from_except
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STD_EXCEPTION_COMMON_LITE(0x500, hardware_interrupt, do_IRQ)
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STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
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STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
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STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
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@ -672,12 +673,6 @@ _GLOBAL(slb_miss_realmode)
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ld r10,PACA_EXSLB+EX_LR(r13)
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ld r3,PACA_EXSLB+EX_R3(r13)
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lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
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#ifdef CONFIG_PPC_ISERIES
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BEGIN_FW_FTR_SECTION
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ld r11,PACALPPACAPTR(r13)
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ld r11,LPPACASRR0(r11) /* get SRR0 value */
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END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
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#endif /* CONFIG_PPC_ISERIES */
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mtlr r10
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@ -690,12 +685,6 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
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mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
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.machine pop
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#ifdef CONFIG_PPC_ISERIES
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BEGIN_FW_FTR_SECTION
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mtspr SPRN_SRR0,r11
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mtspr SPRN_SRR1,r12
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END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
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#endif /* CONFIG_PPC_ISERIES */
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ld r9,PACA_EXSLB+EX_R9(r13)
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ld r10,PACA_EXSLB+EX_R10(r13)
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ld r11,PACA_EXSLB+EX_R11(r13)
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@ -704,13 +693,7 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
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rfid
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b . /* prevent speculative execution */
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2:
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#ifdef CONFIG_PPC_ISERIES
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BEGIN_FW_FTR_SECTION
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b unrecov_slb
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END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
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#endif /* CONFIG_PPC_ISERIES */
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mfspr r11,SPRN_SRR0
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2: mfspr r11,SPRN_SRR0
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ld r10,PACAKBASE(r13)
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LOAD_HANDLER(r10,unrecov_slb)
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mtspr SPRN_SRR0,r10
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@ -727,20 +710,6 @@ unrecov_slb:
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bl .unrecoverable_exception
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b 1b
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.align 7
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.globl hardware_interrupt_common
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.globl hardware_interrupt_entry
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hardware_interrupt_common:
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EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
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FINISH_NAP
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hardware_interrupt_entry:
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DISABLE_INTS
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BEGIN_FTR_SECTION
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bl .ppc64_runlatch_on
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END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl .do_IRQ
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b .ret_from_except_lite
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#ifdef CONFIG_PPC_970_NAP
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power4_fixup_nap:
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@ -913,11 +882,7 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_SLB)
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andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */
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bne 77f /* then don't call hash_page now */
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/*
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* On iSeries, we soft-disable interrupts here, then
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* hard-enable interrupts so that the hash_page code can spin on
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* the hash_table_lock without problems on a shared processor.
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*/
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/* We run with interrupts both soft and hard disabled */
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DISABLE_INTS
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/*
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@ -956,25 +921,11 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_SLB)
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bl .hash_page /* build HPTE if possible */
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cmpdi r3,0 /* see if hash_page succeeded */
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BEGIN_FW_FTR_SECTION
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/*
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* If we had interrupts soft-enabled at the point where the
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* DSI/ISI occurred, and an interrupt came in during hash_page,
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* handle it now.
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* We jump to ret_from_except_lite rather than fast_exception_return
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* because ret_from_except_lite will check for and handle pending
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* interrupts if necessary.
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*/
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beq 13f
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END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
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BEGIN_FW_FTR_SECTION
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/*
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* Here we have interrupts hard-disabled, so it is sufficient
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* to restore paca->{soft,hard}_enable and get out.
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*/
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beq fast_exc_return_irq /* Return from exception on success */
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END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
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/* For a hash failure, we don't bother re-enabling interrupts */
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ble- 12f
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@ -1141,51 +1092,19 @@ _GLOBAL(do_stab_bolted)
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.= 0x7000
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.globl fwnmi_data_area
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fwnmi_data_area:
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#endif /* defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) */
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/* iSeries does not use the FWNMI stuff, so it is safe to put
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* this here, even if we later allow kernels that will boot on
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* both pSeries and iSeries */
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#ifdef CONFIG_PPC_ISERIES
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. = LPARMAP_PHYS
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.globl xLparMap
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xLparMap:
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.quad HvEsidsToMap /* xNumberEsids */
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.quad HvRangesToMap /* xNumberRanges */
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.quad STAB0_PAGE /* xSegmentTableOffs */
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.zero 40 /* xRsvd */
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/* xEsids (HvEsidsToMap entries of 2 quads) */
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.quad PAGE_OFFSET_ESID /* xKernelEsid */
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.quad PAGE_OFFSET_VSID /* xKernelVsid */
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.quad VMALLOC_START_ESID /* xKernelEsid */
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.quad VMALLOC_START_VSID /* xKernelVsid */
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/* xRanges (HvRangesToMap entries of 3 quads) */
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.quad HvPagesToMap /* xPages */
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.quad 0 /* xOffset */
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.quad PAGE_OFFSET_VSID << (SID_SHIFT - HW_PAGE_SHIFT) /* xVPN */
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#endif /* CONFIG_PPC_ISERIES */
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#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
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/* pseries and powernv need to keep the whole page from
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* 0x7000 to 0x8000 free for use by the firmware
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*/
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. = 0x8000
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#endif /* defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) */
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/*
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* Space for CPU0's segment table.
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*
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* On iSeries, the hypervisor must fill in at least one entry before
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* we get control (with relocate on). The address is given to the hv
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* as a page number (see xLparMap above), so this must be at a
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* fixed address (the linker can't compute (u64)&initial_stab >>
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* PAGE_SHIFT).
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*/
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. = STAB0_OFFSET /* 0x8000 */
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/* Space for CPU0's segment table */
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.balign 4096
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.globl initial_stab
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initial_stab:
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.space 4096
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#ifdef CONFIG_PPC_POWERNV
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_GLOBAL(opal_mc_secondary_handler)
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HMT_MEDIUM
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@ -32,7 +32,6 @@
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#include <asm/cputable.h>
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#include <asm/setup.h>
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#include <asm/hvcall.h>
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#include <asm/iseries/lpar_map.h>
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#include <asm/thread_info.h>
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#include <asm/firmware.h>
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#include <asm/page_64.h>
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@ -57,10 +56,6 @@
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* entry in r9 for debugging purposes
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* 2. Secondary processors enter at 0x60 with PIR in gpr3
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*
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* For iSeries:
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* 1. The MMU is on (as it always is for iSeries)
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* 2. The kernel is entered at system_reset_iSeries
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*
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* For Book3E processors:
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* 1. The MMU is on running in AS0 in a state defined in ePAPR
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* 2. The kernel is entered at __start
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@ -93,15 +88,6 @@ __secondary_hold_spinloop:
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__secondary_hold_acknowledge:
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.llong 0x0
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#ifdef CONFIG_PPC_ISERIES
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/*
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* At offset 0x20, there is a pointer to iSeries LPAR data.
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* This is required by the hypervisor
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*/
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. = 0x20
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.llong hvReleaseData-KERNELBASE
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#endif /* CONFIG_PPC_ISERIES */
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#ifdef CONFIG_RELOCATABLE
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/* This flag is set to 1 by a loader if the kernel should run
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* at the loaded address instead of the linked address. This
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@ -582,7 +568,7 @@ _GLOBAL(pmac_secondary_start)
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* 1. Processor number
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* 2. Segment table pointer (virtual address)
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* On entry the following are set:
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* r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
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* r1 = stack pointer (real addr of temp stack)
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* r24 = cpu# (in Linux terms)
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* r13 = paca virtual address
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* SPRG_PACA = paca virtual address
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@ -595,7 +581,7 @@ __secondary_start:
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/* Set thread priority to MEDIUM */
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HMT_MEDIUM
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/* Initialize the kernel stack. Just a repeat for iSeries. */
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/* Initialize the kernel stack */
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LOAD_REG_ADDR(r3, current_set)
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sldi r28,r24,3 /* get current_set[cpu#] */
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ldx r14,r3,r28
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@ -615,20 +601,13 @@ __secondary_start:
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li r7,0
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mtlr r7
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/* Mark interrupts both hard and soft disabled */
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stb r7,PACAHARDIRQEN(r13)
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stb r7,PACASOFTIRQEN(r13)
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/* enable MMU and jump to start_secondary */
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LOAD_REG_ADDR(r3, .start_secondary_prolog)
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LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
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#ifdef CONFIG_PPC_ISERIES
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BEGIN_FW_FTR_SECTION
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ori r4,r4,MSR_EE
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li r8,1
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stb r8,PACAHARDIRQEN(r13)
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END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
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#endif
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BEGIN_FW_FTR_SECTION
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stb r7,PACAHARDIRQEN(r13)
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END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
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stb r7,PACASOFTIRQEN(r13)
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mtspr SPRN_SRR0,r3
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mtspr SPRN_SRR1,r4
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@ -774,17 +753,8 @@ _INIT_GLOBAL(start_here_common)
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bl .setup_system
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/* Load up the kernel context */
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5:
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li r5,0
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5: li r5,0
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stb r5,PACASOFTIRQEN(r13) /* Soft Disabled */
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#ifdef CONFIG_PPC_ISERIES
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BEGIN_FW_FTR_SECTION
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mfmsr r5
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ori r5,r5,MSR_EE /* Hard Enabled on iSeries*/
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mtmsrd r5
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li r5,1
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END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
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#endif
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stb r5,PACAHARDIRQEN(r13) /* Hard Disabled on others */
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bl .start_kernel
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@ -5,7 +5,6 @@
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* Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
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* and Paul Mackerras.
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*
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* Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
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* PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
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*
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* setjmp/longjmp code by Paul Mackerras.
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@ -109,11 +109,6 @@ SECTIONS
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__ptov_table_begin = .;
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*(.ptov_fixup);
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__ptov_table_end = .;
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#ifdef CONFIG_PPC_ISERIES
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__dt_strings_start = .;
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*(.dt_strings);
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__dt_strings_end = .;
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#endif
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}
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.init.setup : AT(ADDR(.init.setup) - LOAD_OFFSET) {
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@ -217,21 +217,6 @@ slb_finish_load:
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* free slot first but that took too long. Unfortunately we
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* dont have any LRU information to help us choose a slot.
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*/
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#ifdef CONFIG_PPC_ISERIES
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BEGIN_FW_FTR_SECTION
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/*
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* On iSeries, the "bolted" stack segment can be cast out on
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* shared processor switch so we need to check for a miss on
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* it and restore it to the right slot.
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*/
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ld r9,PACAKSAVE(r13)
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clrrdi r9,r9,28
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clrrdi r3,r3,28
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li r10,SLB_NUM_BOLTED-1 /* Stack goes in last bolted slot */
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cmpld r9,r3
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beq 3f
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END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
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#endif /* CONFIG_PPC_ISERIES */
|
||||
|
||||
7: ld r10,PACASTABRR(r13)
|
||||
addi r10,r10,1
|
||||
|
|
@ -282,7 +267,6 @@ _GLOBAL(slb_compare_rr_to_size)
|
|||
|
||||
/*
|
||||
* Finish loading of a 1T SLB entry (for the kernel linear mapping) and return.
|
||||
* We assume legacy iSeries will never have 1T segments.
|
||||
*
|
||||
* r3 = EA, r10 = proto-VSID, r11 = flags, clobbers r9
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue