clk: ingenic: Add driver for the TCU clocks
Add driver to support the clocks provided by the Timer/Counter Unit (TCU) of the JZ47xx SoCs from Ingenic. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: Mathieu Malaterre <malat@debian.org> Tested-by: Artur Rojek <contact@artur-rojek.eu> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: Jonathan Corbet <corbet@lwn.net> Cc: Lee Jones <lee.jones@linaro.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-doc@vger.kernel.org Cc: linux-mips@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: od@zcrc.me
This commit is contained in:
Paul Cercueil
Paul Burton
parent
39233b7c61
commit
4f89e4b8f1
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@ -1,5 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0-only
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menu "Ingenic JZ47xx CGU drivers"
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menu "Ingenic SoCs drivers"
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depends on MIPS
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config INGENIC_CGU_COMMON
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@ -45,4 +45,12 @@ config INGENIC_CGU_JZ4780
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If building for a JZ4780 SoC, you want to say Y here.
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config INGENIC_TCU_CLK
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bool "Ingenic JZ47xx TCU clocks driver"
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default MACH_INGENIC
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select MFD_SYSCON
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help
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Support the clocks of the Timer/Counter Unit (TCU) of the Ingenic
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JZ47xx SoCs.
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endmenu
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@ -4,3 +4,4 @@ obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o
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obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o
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obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o
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obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o
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obj-$(CONFIG_INGENIC_TCU_CLK) += tcu.o
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@ -0,0 +1,474 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* JZ47xx SoCs TCU clocks driver
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* Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net>
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clockchips.h>
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#include <linux/mfd/ingenic-tcu.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/syscore_ops.h>
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#include <dt-bindings/clock/ingenic,tcu.h>
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/* 8 channels max + watchdog + OST */
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#define TCU_CLK_COUNT 10
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#undef pr_fmt
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#define pr_fmt(fmt) "ingenic-tcu-clk: " fmt
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enum tcu_clk_parent {
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TCU_PARENT_PCLK,
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TCU_PARENT_RTC,
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TCU_PARENT_EXT,
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};
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struct ingenic_soc_info {
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unsigned int num_channels;
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bool has_ost;
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bool has_tcu_clk;
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};
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struct ingenic_tcu_clk_info {
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struct clk_init_data init_data;
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u8 gate_bit;
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u8 tcsr_reg;
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};
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struct ingenic_tcu_clk {
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struct clk_hw hw;
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unsigned int idx;
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struct ingenic_tcu *tcu;
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const struct ingenic_tcu_clk_info *info;
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};
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struct ingenic_tcu {
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const struct ingenic_soc_info *soc_info;
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struct regmap *map;
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struct clk *clk;
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struct clk_hw_onecell_data *clocks;
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};
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static struct ingenic_tcu *ingenic_tcu;
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static inline struct ingenic_tcu_clk *to_tcu_clk(struct clk_hw *hw)
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{
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return container_of(hw, struct ingenic_tcu_clk, hw);
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}
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static int ingenic_tcu_enable(struct clk_hw *hw)
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{
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struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
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const struct ingenic_tcu_clk_info *info = tcu_clk->info;
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struct ingenic_tcu *tcu = tcu_clk->tcu;
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regmap_write(tcu->map, TCU_REG_TSCR, BIT(info->gate_bit));
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return 0;
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}
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static void ingenic_tcu_disable(struct clk_hw *hw)
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{
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struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
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const struct ingenic_tcu_clk_info *info = tcu_clk->info;
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struct ingenic_tcu *tcu = tcu_clk->tcu;
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regmap_write(tcu->map, TCU_REG_TSSR, BIT(info->gate_bit));
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}
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static int ingenic_tcu_is_enabled(struct clk_hw *hw)
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{
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struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
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const struct ingenic_tcu_clk_info *info = tcu_clk->info;
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unsigned int value;
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regmap_read(tcu_clk->tcu->map, TCU_REG_TSR, &value);
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return !(value & BIT(info->gate_bit));
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}
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static bool ingenic_tcu_enable_regs(struct clk_hw *hw)
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{
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struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
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const struct ingenic_tcu_clk_info *info = tcu_clk->info;
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struct ingenic_tcu *tcu = tcu_clk->tcu;
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bool enabled = false;
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/*
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* If the SoC has no global TCU clock, we must ungate the channel's
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* clock to be able to access its registers.
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* If we have a TCU clock, it will be enabled automatically as it has
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* been attached to the regmap.
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*/
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if (!tcu->clk) {
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enabled = !!ingenic_tcu_is_enabled(hw);
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regmap_write(tcu->map, TCU_REG_TSCR, BIT(info->gate_bit));
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}
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return enabled;
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}
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static void ingenic_tcu_disable_regs(struct clk_hw *hw)
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{
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struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
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const struct ingenic_tcu_clk_info *info = tcu_clk->info;
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struct ingenic_tcu *tcu = tcu_clk->tcu;
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if (!tcu->clk)
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regmap_write(tcu->map, TCU_REG_TSSR, BIT(info->gate_bit));
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}
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static u8 ingenic_tcu_get_parent(struct clk_hw *hw)
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{
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struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
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const struct ingenic_tcu_clk_info *info = tcu_clk->info;
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unsigned int val = 0;
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int ret;
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ret = regmap_read(tcu_clk->tcu->map, info->tcsr_reg, &val);
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WARN_ONCE(ret < 0, "Unable to read TCSR %d", tcu_clk->idx);
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return ffs(val & TCU_TCSR_PARENT_CLOCK_MASK) - 1;
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}
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static int ingenic_tcu_set_parent(struct clk_hw *hw, u8 idx)
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{
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struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
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const struct ingenic_tcu_clk_info *info = tcu_clk->info;
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bool was_enabled;
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int ret;
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was_enabled = ingenic_tcu_enable_regs(hw);
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ret = regmap_update_bits(tcu_clk->tcu->map, info->tcsr_reg,
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TCU_TCSR_PARENT_CLOCK_MASK, BIT(idx));
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WARN_ONCE(ret < 0, "Unable to update TCSR %d", tcu_clk->idx);
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if (!was_enabled)
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ingenic_tcu_disable_regs(hw);
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return 0;
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}
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static unsigned long ingenic_tcu_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
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const struct ingenic_tcu_clk_info *info = tcu_clk->info;
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unsigned int prescale;
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int ret;
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ret = regmap_read(tcu_clk->tcu->map, info->tcsr_reg, &prescale);
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WARN_ONCE(ret < 0, "Unable to read TCSR %d", tcu_clk->idx);
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prescale = (prescale & TCU_TCSR_PRESCALE_MASK) >> TCU_TCSR_PRESCALE_LSB;
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return parent_rate >> (prescale * 2);
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}
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static u8 ingenic_tcu_get_prescale(unsigned long rate, unsigned long req_rate)
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{
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u8 prescale;
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for (prescale = 0; prescale < 5; prescale++)
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if ((rate >> (prescale * 2)) <= req_rate)
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return prescale;
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return 5; /* /1024 divider */
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}
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static long ingenic_tcu_round_rate(struct clk_hw *hw, unsigned long req_rate,
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unsigned long *parent_rate)
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{
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unsigned long rate = *parent_rate;
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u8 prescale;
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if (req_rate > rate)
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return -EINVAL;
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prescale = ingenic_tcu_get_prescale(rate, req_rate);
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return rate >> (prescale * 2);
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}
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static int ingenic_tcu_set_rate(struct clk_hw *hw, unsigned long req_rate,
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unsigned long parent_rate)
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{
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struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
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const struct ingenic_tcu_clk_info *info = tcu_clk->info;
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u8 prescale = ingenic_tcu_get_prescale(parent_rate, req_rate);
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bool was_enabled;
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int ret;
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was_enabled = ingenic_tcu_enable_regs(hw);
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ret = regmap_update_bits(tcu_clk->tcu->map, info->tcsr_reg,
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TCU_TCSR_PRESCALE_MASK,
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prescale << TCU_TCSR_PRESCALE_LSB);
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WARN_ONCE(ret < 0, "Unable to update TCSR %d", tcu_clk->idx);
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if (!was_enabled)
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ingenic_tcu_disable_regs(hw);
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return 0;
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}
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static const struct clk_ops ingenic_tcu_clk_ops = {
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.get_parent = ingenic_tcu_get_parent,
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.set_parent = ingenic_tcu_set_parent,
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.recalc_rate = ingenic_tcu_recalc_rate,
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.round_rate = ingenic_tcu_round_rate,
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.set_rate = ingenic_tcu_set_rate,
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.enable = ingenic_tcu_enable,
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.disable = ingenic_tcu_disable,
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.is_enabled = ingenic_tcu_is_enabled,
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};
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static const char * const ingenic_tcu_timer_parents[] = {
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[TCU_PARENT_PCLK] = "pclk",
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[TCU_PARENT_RTC] = "rtc",
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[TCU_PARENT_EXT] = "ext",
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};
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#define DEF_TIMER(_name, _gate_bit, _tcsr) \
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{ \
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.init_data = { \
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.name = _name, \
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.parent_names = ingenic_tcu_timer_parents, \
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.num_parents = ARRAY_SIZE(ingenic_tcu_timer_parents),\
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.ops = &ingenic_tcu_clk_ops, \
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.flags = CLK_SET_RATE_UNGATE, \
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}, \
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.gate_bit = _gate_bit, \
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.tcsr_reg = _tcsr, \
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}
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static const struct ingenic_tcu_clk_info ingenic_tcu_clk_info[] = {
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[TCU_CLK_TIMER0] = DEF_TIMER("timer0", 0, TCU_REG_TCSRc(0)),
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[TCU_CLK_TIMER1] = DEF_TIMER("timer1", 1, TCU_REG_TCSRc(1)),
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[TCU_CLK_TIMER2] = DEF_TIMER("timer2", 2, TCU_REG_TCSRc(2)),
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[TCU_CLK_TIMER3] = DEF_TIMER("timer3", 3, TCU_REG_TCSRc(3)),
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[TCU_CLK_TIMER4] = DEF_TIMER("timer4", 4, TCU_REG_TCSRc(4)),
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[TCU_CLK_TIMER5] = DEF_TIMER("timer5", 5, TCU_REG_TCSRc(5)),
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[TCU_CLK_TIMER6] = DEF_TIMER("timer6", 6, TCU_REG_TCSRc(6)),
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[TCU_CLK_TIMER7] = DEF_TIMER("timer7", 7, TCU_REG_TCSRc(7)),
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};
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static const struct ingenic_tcu_clk_info ingenic_tcu_watchdog_clk_info =
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DEF_TIMER("wdt", 16, TCU_REG_WDT_TCSR);
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static const struct ingenic_tcu_clk_info ingenic_tcu_ost_clk_info =
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DEF_TIMER("ost", 15, TCU_REG_OST_TCSR);
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#undef DEF_TIMER
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static int __init ingenic_tcu_register_clock(struct ingenic_tcu *tcu,
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unsigned int idx, enum tcu_clk_parent parent,
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const struct ingenic_tcu_clk_info *info,
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struct clk_hw_onecell_data *clocks)
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{
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struct ingenic_tcu_clk *tcu_clk;
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int err;
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tcu_clk = kzalloc(sizeof(*tcu_clk), GFP_KERNEL);
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if (!tcu_clk)
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return -ENOMEM;
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tcu_clk->hw.init = &info->init_data;
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tcu_clk->idx = idx;
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tcu_clk->info = info;
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tcu_clk->tcu = tcu;
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/* Reset channel and clock divider, set default parent */
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ingenic_tcu_enable_regs(&tcu_clk->hw);
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regmap_update_bits(tcu->map, info->tcsr_reg, 0xffff, BIT(parent));
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ingenic_tcu_disable_regs(&tcu_clk->hw);
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err = clk_hw_register(NULL, &tcu_clk->hw);
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if (err) {
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kfree(tcu_clk);
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return err;
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}
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clocks->hws[idx] = &tcu_clk->hw;
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return 0;
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}
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static const struct ingenic_soc_info jz4740_soc_info = {
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.num_channels = 8,
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.has_ost = false,
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.has_tcu_clk = true,
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};
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static const struct ingenic_soc_info jz4725b_soc_info = {
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.num_channels = 6,
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.has_ost = true,
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.has_tcu_clk = true,
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};
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static const struct ingenic_soc_info jz4770_soc_info = {
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.num_channels = 8,
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.has_ost = true,
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.has_tcu_clk = false,
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};
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static const struct of_device_id ingenic_tcu_of_match[] __initconst = {
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{ .compatible = "ingenic,jz4740-tcu", .data = &jz4740_soc_info, },
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{ .compatible = "ingenic,jz4725b-tcu", .data = &jz4725b_soc_info, },
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{ .compatible = "ingenic,jz4770-tcu", .data = &jz4770_soc_info, },
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{ /* sentinel */ }
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};
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static int __init ingenic_tcu_probe(struct device_node *np)
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{
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const struct of_device_id *id = of_match_node(ingenic_tcu_of_match, np);
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struct ingenic_tcu *tcu;
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struct regmap *map;
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unsigned int i;
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int ret;
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map = device_node_to_regmap(np);
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if (IS_ERR(map))
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return PTR_ERR(map);
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tcu = kzalloc(sizeof(*tcu), GFP_KERNEL);
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if (!tcu)
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return -ENOMEM;
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tcu->map = map;
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tcu->soc_info = id->data;
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if (tcu->soc_info->has_tcu_clk) {
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tcu->clk = of_clk_get_by_name(np, "tcu");
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if (IS_ERR(tcu->clk)) {
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ret = PTR_ERR(tcu->clk);
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pr_crit("Cannot get TCU clock\n");
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goto err_free_tcu;
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}
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ret = clk_prepare_enable(tcu->clk);
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if (ret) {
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pr_crit("Unable to enable TCU clock\n");
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goto err_put_clk;
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}
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}
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tcu->clocks = kzalloc(sizeof(*tcu->clocks) +
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sizeof(*tcu->clocks->hws) * TCU_CLK_COUNT,
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GFP_KERNEL);
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if (!tcu->clocks) {
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ret = -ENOMEM;
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goto err_clk_disable;
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}
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tcu->clocks->num = TCU_CLK_COUNT;
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for (i = 0; i < tcu->soc_info->num_channels; i++) {
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ret = ingenic_tcu_register_clock(tcu, i, TCU_PARENT_EXT,
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&ingenic_tcu_clk_info[i],
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tcu->clocks);
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if (ret) {
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pr_crit("cannot register clock %d\n", i);
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goto err_unregister_timer_clocks;
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}
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}
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/*
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* We set EXT as the default parent clock for all the TCU clocks
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* except for the watchdog one, where we set the RTC clock as the
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* parent. Since the EXT and PCLK are much faster than the RTC clock,
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* the watchdog would kick after a maximum time of 5s, and we might
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* want a slower kicking time.
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*/
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||||
ret = ingenic_tcu_register_clock(tcu, TCU_CLK_WDT, TCU_PARENT_RTC,
|
||||
&ingenic_tcu_watchdog_clk_info,
|
||||
tcu->clocks);
|
||||
if (ret) {
|
||||
pr_crit("cannot register watchdog clock\n");
|
||||
goto err_unregister_timer_clocks;
|
||||
}
|
||||
|
||||
if (tcu->soc_info->has_ost) {
|
||||
ret = ingenic_tcu_register_clock(tcu, TCU_CLK_OST,
|
||||
TCU_PARENT_EXT,
|
||||
&ingenic_tcu_ost_clk_info,
|
||||
tcu->clocks);
|
||||
if (ret) {
|
||||
pr_crit("cannot register ost clock\n");
|
||||
goto err_unregister_watchdog_clock;
|
||||
}
|
||||
}
|
||||
|
||||
ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, tcu->clocks);
|
||||
if (ret) {
|
||||
pr_crit("cannot add OF clock provider\n");
|
||||
goto err_unregister_ost_clock;
|
||||
}
|
||||
|
||||
ingenic_tcu = tcu;
|
||||
|
||||
return 0;
|
||||
|
||||
err_unregister_ost_clock:
|
||||
if (tcu->soc_info->has_ost)
|
||||
clk_hw_unregister(tcu->clocks->hws[i + 1]);
|
||||
err_unregister_watchdog_clock:
|
||||
clk_hw_unregister(tcu->clocks->hws[i]);
|
||||
err_unregister_timer_clocks:
|
||||
for (i = 0; i < tcu->clocks->num; i++)
|
||||
if (tcu->clocks->hws[i])
|
||||
clk_hw_unregister(tcu->clocks->hws[i]);
|
||||
kfree(tcu->clocks);
|
||||
err_clk_disable:
|
||||
if (tcu->soc_info->has_tcu_clk)
|
||||
clk_disable_unprepare(tcu->clk);
|
||||
err_put_clk:
|
||||
if (tcu->soc_info->has_tcu_clk)
|
||||
clk_put(tcu->clk);
|
||||
err_free_tcu:
|
||||
kfree(tcu);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __maybe_unused tcu_pm_suspend(void)
|
||||
{
|
||||
struct ingenic_tcu *tcu = ingenic_tcu;
|
||||
|
||||
if (tcu->clk)
|
||||
clk_disable(tcu->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __maybe_unused tcu_pm_resume(void)
|
||||
{
|
||||
struct ingenic_tcu *tcu = ingenic_tcu;
|
||||
|
||||
if (tcu->clk)
|
||||
clk_enable(tcu->clk);
|
||||
}
|
||||
|
||||
static struct syscore_ops __maybe_unused tcu_pm_ops = {
|
||||
.suspend = tcu_pm_suspend,
|
||||
.resume = tcu_pm_resume,
|
||||
};
|
||||
|
||||
static void __init ingenic_tcu_init(struct device_node *np)
|
||||
{
|
||||
int ret = ingenic_tcu_probe(np);
|
||||
|
||||
if (ret)
|
||||
pr_crit("Failed to initialize TCU clocks: %d\n", ret);
|
||||
|
||||
if (IS_ENABLED(CONFIG_PM_SLEEP))
|
||||
register_syscore_ops(&tcu_pm_ops);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-tcu", ingenic_tcu_init);
|
||||
CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-tcu", ingenic_tcu_init);
|
||||
CLK_OF_DECLARE_DRIVER(jz4770_cgu, "ingenic,jz4770-tcu", ingenic_tcu_init);
|
||||
Loading…
Reference in New Issue