MN10300: Implement atomic ops using atomic ops unit
Implement atomic ops using the atomic ops unit available in the AM34 CPU. This allows the equivalent of the LL/SC instructions to be found on other CPUs. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: David Howells <dhowells@redhat.com>
This commit is contained in:
Mark Salter
David Howells
parent
278d91c460
commit
4f81ca1353
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/* MN10300 Atomic counter operations
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*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#ifndef _ASM_ATOMIC_H
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#define _ASM_ATOMIC_H
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#include <asm/irqflags.h>
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#ifndef __ASSEMBLY__
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#ifdef CONFIG_SMP
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#ifdef CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
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static inline
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unsigned long __xchg(volatile unsigned long *m, unsigned long val)
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{
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unsigned long status;
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unsigned long oldval;
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asm volatile(
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"1: mov %4,(_AAR,%3) \n"
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" mov (_ADR,%3),%1 \n"
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" mov %5,(_ADR,%3) \n"
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" mov (_ADR,%3),%0 \n" /* flush */
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" mov (_ASR,%3),%0 \n"
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" or %0,%0 \n"
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" bne 1b \n"
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: "=&r"(status), "=&r"(oldval), "=m"(*m)
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: "a"(ATOMIC_OPS_BASE_ADDR), "r"(m), "r"(val)
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: "memory", "cc");
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return oldval;
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}
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static inline unsigned long __cmpxchg(volatile unsigned long *m,
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unsigned long old, unsigned long new)
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{
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unsigned long status;
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unsigned long oldval;
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asm volatile(
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"1: mov %4,(_AAR,%3) \n"
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" mov (_ADR,%3),%1 \n"
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" cmp %5,%1 \n"
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" bne 2f \n"
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" mov %6,(_ADR,%3) \n"
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"2: mov (_ADR,%3),%0 \n" /* flush */
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" mov (_ASR,%3),%0 \n"
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" or %0,%0 \n"
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" bne 1b \n"
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: "=&r"(status), "=&r"(oldval), "=m"(*m)
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: "a"(ATOMIC_OPS_BASE_ADDR), "r"(m),
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"r"(old), "r"(new)
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: "memory", "cc");
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return oldval;
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}
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#else /* CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT */
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#error "No SMP atomic operation support!"
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#endif /* CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT */
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#else /* CONFIG_SMP */
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/*
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* Emulate xchg for non-SMP MN10300
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*/
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struct __xchg_dummy { unsigned long a[100]; };
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#define __xg(x) ((struct __xchg_dummy *)(x))
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static inline
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unsigned long __xchg(volatile unsigned long *m, unsigned long val)
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{
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unsigned long oldval;
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unsigned long flags;
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flags = arch_local_cli_save();
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oldval = *m;
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*m = val;
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arch_local_irq_restore(flags);
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return oldval;
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}
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/*
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* Emulate cmpxchg for non-SMP MN10300
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*/
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static inline unsigned long __cmpxchg(volatile unsigned long *m,
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unsigned long old, unsigned long new)
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{
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unsigned long oldval;
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unsigned long flags;
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flags = arch_local_cli_save();
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oldval = *m;
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if (oldval == old)
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*m = new;
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arch_local_irq_restore(flags);
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return oldval;
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}
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#endif /* CONFIG_SMP */
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#define xchg(ptr, v) \
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((__typeof__(*(ptr))) __xchg((unsigned long *)(ptr), \
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(unsigned long)(v)))
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#define cmpxchg(ptr, o, n) \
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((__typeof__(*(ptr))) __cmpxchg((unsigned long *)(ptr), \
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(unsigned long)(o), \
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(unsigned long)(n)))
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#define atomic_xchg(ptr, v) (xchg(&(ptr)->counter, (v)))
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#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), (old), (new)))
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#endif /* !__ASSEMBLY__ */
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#ifndef CONFIG_SMP
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#include <asm-generic/atomic.h>
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#else
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/*
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* Atomic operations that C can't guarantee us. Useful for
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* resource counting etc..
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*/
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#define ATOMIC_INIT(i) { (i) }
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#ifdef __KERNEL__
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/**
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* atomic_read - read atomic variable
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* @v: pointer of type atomic_t
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*
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* Atomically reads the value of @v. Note that the guaranteed
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* useful range of an atomic_t is only 24 bits.
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*/
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#define atomic_read(v) ((v)->counter)
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/**
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* atomic_set - set atomic variable
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* @v: pointer of type atomic_t
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* @i: required value
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*
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* Atomically sets the value of @v to @i. Note that the guaranteed
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* useful range of an atomic_t is only 24 bits.
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*/
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#define atomic_set(v, i) (((v)->counter) = (i))
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/**
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* atomic_add_return - add integer to atomic variable
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* @i: integer value to add
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* @v: pointer of type atomic_t
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*
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* Atomically adds @i to @v and returns the result
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* Note that the guaranteed useful range of an atomic_t is only 24 bits.
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*/
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static inline int atomic_add_return(int i, atomic_t *v)
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{
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int retval;
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#ifdef CONFIG_SMP
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int status;
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asm volatile(
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"1: mov %4,(_AAR,%3) \n"
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" mov (_ADR,%3),%1 \n"
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" add %5,%1 \n"
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" mov %1,(_ADR,%3) \n"
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" mov (_ADR,%3),%0 \n" /* flush */
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" mov (_ASR,%3),%0 \n"
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" or %0,%0 \n"
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" bne 1b \n"
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: "=&r"(status), "=&r"(retval), "=m"(v->counter)
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: "a"(ATOMIC_OPS_BASE_ADDR), "r"(&v->counter), "r"(i)
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: "memory", "cc");
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#else
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unsigned long flags;
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flags = arch_local_cli_save();
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retval = v->counter;
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retval += i;
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v->counter = retval;
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arch_local_irq_restore(flags);
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#endif
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return retval;
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}
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/**
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* atomic_sub_return - subtract integer from atomic variable
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* @i: integer value to subtract
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* @v: pointer of type atomic_t
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*
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* Atomically subtracts @i from @v and returns the result
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* Note that the guaranteed useful range of an atomic_t is only 24 bits.
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*/
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static inline int atomic_sub_return(int i, atomic_t *v)
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{
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int retval;
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#ifdef CONFIG_SMP
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int status;
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asm volatile(
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"1: mov %4,(_AAR,%3) \n"
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" mov (_ADR,%3),%1 \n"
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" sub %5,%1 \n"
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" mov %1,(_ADR,%3) \n"
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" mov (_ADR,%3),%0 \n" /* flush */
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" mov (_ASR,%3),%0 \n"
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" or %0,%0 \n"
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" bne 1b \n"
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: "=&r"(status), "=&r"(retval), "=m"(v->counter)
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: "a"(ATOMIC_OPS_BASE_ADDR), "r"(&v->counter), "r"(i)
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: "memory", "cc");
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#else
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unsigned long flags;
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flags = arch_local_cli_save();
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retval = v->counter;
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retval -= i;
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v->counter = retval;
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arch_local_irq_restore(flags);
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#endif
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return retval;
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}
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static inline int atomic_add_negative(int i, atomic_t *v)
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{
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return atomic_add_return(i, v) < 0;
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}
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static inline void atomic_add(int i, atomic_t *v)
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{
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atomic_add_return(i, v);
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}
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static inline void atomic_sub(int i, atomic_t *v)
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{
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atomic_sub_return(i, v);
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}
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static inline void atomic_inc(atomic_t *v)
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{
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atomic_add_return(1, v);
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}
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static inline void atomic_dec(atomic_t *v)
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{
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atomic_sub_return(1, v);
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}
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#define atomic_dec_return(v) atomic_sub_return(1, (v))
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#define atomic_inc_return(v) atomic_add_return(1, (v))
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#define atomic_sub_and_test(i, v) (atomic_sub_return((i), (v)) == 0)
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#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
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#define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0)
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#define atomic_add_unless(v, a, u) \
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({ \
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int c, old; \
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c = atomic_read(v); \
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while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
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c = old; \
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c != (u); \
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})
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#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
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/**
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* atomic_clear_mask - Atomically clear bits in memory
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* @mask: Mask of the bits to be cleared
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* @v: pointer to word in memory
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*
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* Atomically clears the bits set in mask from the memory word specified.
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*/
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static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
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{
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#ifdef CONFIG_SMP
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int status;
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asm volatile(
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"1: mov %3,(_AAR,%2) \n"
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" mov (_ADR,%2),%0 \n"
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" and %4,%0 \n"
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" mov %0,(_ADR,%2) \n"
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" mov (_ADR,%2),%0 \n" /* flush */
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" mov (_ASR,%2),%0 \n"
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" or %0,%0 \n"
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" bne 1b \n"
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: "=&r"(status), "=m"(*addr)
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: "a"(ATOMIC_OPS_BASE_ADDR), "r"(addr), "r"(~mask)
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: "memory", "cc");
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#else
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unsigned long flags;
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mask = ~mask;
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flags = arch_local_cli_save();
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*addr &= mask;
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arch_local_irq_restore(flags);
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#endif
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}
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/**
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* atomic_set_mask - Atomically set bits in memory
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* @mask: Mask of the bits to be set
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* @v: pointer to word in memory
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*
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* Atomically sets the bits set in mask from the memory word specified.
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*/
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static inline void atomic_set_mask(unsigned long mask, unsigned long *addr)
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{
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#ifdef CONFIG_SMP
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int status;
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asm volatile(
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"1: mov %3,(_AAR,%2) \n"
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" mov (_ADR,%2),%0 \n"
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" or %4,%0 \n"
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" mov %0,(_ADR,%2) \n"
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" mov (_ADR,%2),%0 \n" /* flush */
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" mov (_ASR,%2),%0 \n"
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" or %0,%0 \n"
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" bne 1b \n"
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: "=&r"(status), "=m"(*addr)
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: "a"(ATOMIC_OPS_BASE_ADDR), "r"(addr), "r"(mask)
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: "memory", "cc");
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#else
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unsigned long flags;
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flags = arch_local_cli_save();
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*addr |= mask;
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arch_local_irq_restore(flags);
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#endif
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}
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/* Atomic operations are already serializing on MN10300??? */
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#define smp_mb__before_atomic_dec() barrier()
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#define smp_mb__after_atomic_dec() barrier()
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#define smp_mb__before_atomic_inc() barrier()
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#define smp_mb__after_atomic_inc() barrier()
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#include <asm-generic/atomic-long.h>
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#endif /* __KERNEL__ */
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#endif /* CONFIG_SMP */
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#endif /* _ASM_ATOMIC_H */
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@ -18,6 +18,7 @@
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#include <linux/kernel.h>
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#include <linux/irqflags.h>
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#include <asm/atomic.h>
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#if !defined(CONFIG_LAZY_SAVE_FPU)
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struct fpu_state_struct;
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@ -96,52 +97,5 @@ do { \
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#define read_barrier_depends() do {} while (0)
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#define smp_read_barrier_depends() do {} while (0)
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/*****************************************************************************/
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/*
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* MN10300 doesn't actually have an exchange instruction
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*/
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#ifndef __ASSEMBLY__
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struct __xchg_dummy { unsigned long a[100]; };
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#define __xg(x) ((struct __xchg_dummy *)(x))
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static inline
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unsigned long __xchg(volatile unsigned long *m, unsigned long val)
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{
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unsigned long retval;
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unsigned long flags;
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local_irq_save(flags);
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retval = *m;
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*m = val;
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local_irq_restore(flags);
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return retval;
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}
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#define xchg(ptr, v) \
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((__typeof__(*(ptr))) __xchg((unsigned long *)(ptr), \
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(unsigned long)(v)))
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static inline unsigned long __cmpxchg(volatile unsigned long *m,
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unsigned long old, unsigned long new)
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{
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unsigned long retval;
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unsigned long flags;
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local_irq_save(flags);
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retval = *m;
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if (retval == old)
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*m = new;
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local_irq_restore(flags);
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return retval;
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}
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#define cmpxchg(ptr, o, n) \
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((__typeof__(*(ptr))) __cmpxchg((unsigned long *)(ptr), \
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(unsigned long)(o), \
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(unsigned long)(n)))
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#endif /* !__ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_SYSTEM_H */
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