irqchip core changes for v3.17 (incremental #2)
- or1k-pic
- Migrate driver from arch/openrisc
- crossbar
- cleanup series
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Merge tag 'irqchip-core-3.17-2' of git://git.infradead.org/users/jcooper/linux into irq/core
irqchip core changes form Jason Cooper
* or1k-pic: Migrate driver from arch/openrisc
* crossbar: Cleanup series
This commit is contained in:
Thomas Gleixner
commit
4f808391df
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@ -10,6 +10,7 @@ Required properties:
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- compatible : Should be "ti,irq-crossbar"
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- reg: Base address and the size of the crossbar registers.
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- ti,max-irqs: Total number of irqs available at the interrupt controller.
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- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
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- ti,reg-size: Size of a individual register in bytes. Every individual
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register is assumed to be of same size. Valid sizes are 1, 2, 4.
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- ti,irqs-reserved: List of the reserved irq lines that are not muxed using
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@ -17,11 +18,46 @@ Required properties:
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so crossbar bar driver should not consider them as free
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lines.
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Optional properties:
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- ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for
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SOC-specific hard-wiring of those irqs which unexpectedly bypasses the
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crossbar. These irqs have a crossbar register, but still cannot be used.
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- ti,irqs-safe-map: integer which maps to a safe configuration to use
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when the interrupt controller irq is unused (when not provided, default is 0)
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Examples:
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crossbar_mpu: @4a020000 {
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compatible = "ti,irq-crossbar";
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reg = <0x4a002a48 0x130>;
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ti,max-irqs = <160>;
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ti,max-crossbar-sources = <400>;
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ti,reg-size = <2>;
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ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;
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ti,irqs-skip = <10 133 139 140>;
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};
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Consumer:
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========
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See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and
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Documentation/devicetree/bindings/arm/gic.txt for further details.
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An interrupt consumer on an SoC using crossbar will use:
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interrupts = <GIC_SPI request_number interrupt_level>
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When the request number is between 0 to that described by
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"ti,max-crossbar-sources", it is assumed to be a crossbar mapping. If the
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request_number is greater than "ti,max-crossbar-sources", then it is mapped as a
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quirky hardware mapping direct to GIC.
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Example:
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device_x@0x4a023000 {
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/* Crossbar 8 used */
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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...
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};
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device_y@0x4a033000 {
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/* Direct mapped GIC SPI 1 used */
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interrupts = <GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH>;
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...
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};
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@ -0,0 +1,23 @@
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OpenRISC 1000 Programmable Interrupt Controller
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Required properties:
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- compatible : should be "opencores,or1k-pic-level" for variants with
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level triggered interrupt lines, "opencores,or1k-pic-edge" for variants with
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edge triggered interrupt lines or "opencores,or1200-pic" for machines
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with the non-spec compliant or1200 type implementation.
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"opencores,or1k-pic" is also provided as an alias to "opencores,or1200-pic",
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but this is only for backwards compatibility.
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt source. The value shall be 1.
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Example:
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intc: interrupt-controller {
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compatible = "opencores,or1k-pic-level";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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@ -22,6 +22,7 @@ config OPENRISC
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select GENERIC_STRNLEN_USER
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select MODULES_USE_ELF_RELA
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select HAVE_DEBUG_STACKOVERFLOW
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select OR1K_PIC
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config MMU
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def_bool y
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@ -24,4 +24,7 @@
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#define NO_IRQ (-1)
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void handle_IRQ(unsigned int, struct pt_regs *);
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extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
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#endif /* __ASM_OPENRISC_IRQ_H__ */
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@ -16,11 +16,10 @@
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/ftrace.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/export.h>
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#include <linux/irqdomain.h>
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#include <linux/irqflags.h>
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/* read interrupt enabled status */
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@ -37,150 +36,31 @@ void arch_local_irq_restore(unsigned long flags)
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}
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EXPORT_SYMBOL(arch_local_irq_restore);
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/* OR1K PIC implementation */
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/* We're a couple of cycles faster than the generic implementations with
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* these 'fast' versions.
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*/
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static void or1k_pic_mask(struct irq_data *data)
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{
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mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));
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}
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static void or1k_pic_unmask(struct irq_data *data)
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{
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mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (1UL << data->hwirq));
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}
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static void or1k_pic_ack(struct irq_data *data)
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{
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/* EDGE-triggered interrupts need to be ack'ed in order to clear
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* the latch.
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* LEVEL-triggered interrupts do not need to be ack'ed; however,
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* ack'ing the interrupt has no ill-effect and is quicker than
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* trying to figure out what type it is...
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*/
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/* The OpenRISC 1000 spec says to write a 1 to the bit to ack the
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* interrupt, but the OR1200 does this backwards and requires a 0
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* to be written...
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*/
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#ifdef CONFIG_OR1K_1200
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/* There are two oddities with the OR1200 PIC implementation:
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* i) LEVEL-triggered interrupts are latched and need to be cleared
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* ii) the interrupt latch is cleared by writing a 0 to the bit,
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* as opposed to a 1 as mandated by the spec
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*/
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mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq));
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#else
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WARN(1, "Interrupt handling possibly broken\n");
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mtspr(SPR_PICSR, (1UL << data->hwirq));
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#endif
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}
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static void or1k_pic_mask_ack(struct irq_data *data)
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{
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/* Comments for pic_ack apply here, too */
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#ifdef CONFIG_OR1K_1200
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mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));
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mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq));
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#else
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WARN(1, "Interrupt handling possibly broken\n");
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mtspr(SPR_PICMR, (1UL << data->hwirq));
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mtspr(SPR_PICSR, (1UL << data->hwirq));
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#endif
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}
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#if 0
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static int or1k_pic_set_type(struct irq_data *data, unsigned int flow_type)
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{
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/* There's nothing to do in the PIC configuration when changing
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* flow type. Level and edge-triggered interrupts are both
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* supported, but it's PIC-implementation specific which type
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* is handled. */
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return irq_setup_alt_chip(data, flow_type);
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}
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#endif
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static struct irq_chip or1k_dev = {
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.name = "or1k-PIC",
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.irq_unmask = or1k_pic_unmask,
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.irq_mask = or1k_pic_mask,
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.irq_ack = or1k_pic_ack,
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.irq_mask_ack = or1k_pic_mask_ack,
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};
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static struct irq_domain *root_domain;
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static inline int pic_get_irq(int first)
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{
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int hwirq;
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hwirq = ffs(mfspr(SPR_PICSR) >> first);
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if (!hwirq)
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return NO_IRQ;
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else
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hwirq = hwirq + first -1;
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return irq_find_mapping(root_domain, hwirq);
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}
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static int or1k_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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{
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irq_set_chip_and_handler_name(irq, &or1k_dev,
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handle_level_irq, "level");
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irq_set_status_flags(irq, IRQ_LEVEL | IRQ_NOPROBE);
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return 0;
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}
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static const struct irq_domain_ops or1k_irq_domain_ops = {
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.xlate = irq_domain_xlate_onecell,
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.map = or1k_map,
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};
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/*
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* This sets up the IRQ domain for the PIC built in to the OpenRISC
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* 1000 CPU. This is the "root" domain as these are the interrupts
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* that directly trigger an exception in the CPU.
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*/
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static void __init or1k_irq_init(void)
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{
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struct device_node *intc = NULL;
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/* The interrupt controller device node is mandatory */
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intc = of_find_compatible_node(NULL, NULL, "opencores,or1k-pic");
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BUG_ON(!intc);
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/* Disable all interrupts until explicitly requested */
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mtspr(SPR_PICMR, (0UL));
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root_domain = irq_domain_add_linear(intc, 32,
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&or1k_irq_domain_ops, NULL);
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}
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void __init init_IRQ(void)
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{
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or1k_irq_init();
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irqchip_init();
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}
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void __irq_entry do_IRQ(struct pt_regs *regs)
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static void (*handle_arch_irq)(struct pt_regs *);
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void __init set_handle_irq(void (*handle_irq)(struct pt_regs *))
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{
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handle_arch_irq = handle_irq;
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}
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void handle_IRQ(unsigned int irq, struct pt_regs *regs)
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{
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int irq = -1;
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struct pt_regs *old_regs = set_irq_regs(regs);
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irq_enter();
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while ((irq = pic_get_irq(irq + 1)) != NO_IRQ)
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generic_handle_irq(irq);
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generic_handle_irq(irq);
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irq_exit();
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set_irq_regs(old_regs);
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}
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void __irq_entry do_IRQ(struct pt_regs *regs)
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{
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handle_arch_irq(regs);
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}
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@ -53,6 +53,10 @@ config CLPS711X_IRQCHIP
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select SPARSE_IRQ
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default y
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config OR1K_PIC
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bool
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select IRQ_DOMAIN
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config ORION_IRQCHIP
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bool
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select IRQ_DOMAIN
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@ -11,6 +11,7 @@ obj-$(CONFIG_METAG) += irq-metag-ext.o
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obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
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obj-$(CONFIG_ARCH_MOXART) += irq-moxart.o
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obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o
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obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o
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obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o
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obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o
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obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi-nmi.o
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|
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@ -15,22 +15,31 @@
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#include <linux/of_irq.h>
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#include <linux/slab.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/irqchip/irq-crossbar.h>
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#define IRQ_FREE -1
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#define IRQ_RESERVED -2
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#define IRQ_SKIP -3
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#define GIC_IRQ_START 32
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/*
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/**
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* struct crossbar_device - crossbar device description
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* @int_max: maximum number of supported interrupts
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* @safe_map: safe default value to initialize the crossbar
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* @max_crossbar_sources: Maximum number of crossbar sources
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* @irq_map: array of interrupts to crossbar number mapping
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* @crossbar_base: crossbar base address
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* @register_offsets: offsets for each irq number
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* @write: register write function pointer
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*/
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struct crossbar_device {
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uint int_max;
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uint safe_map;
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uint max_crossbar_sources;
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uint *irq_map;
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void __iomem *crossbar_base;
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int *register_offsets;
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void (*write) (int, int);
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void (*write)(int, int);
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};
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|
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static struct crossbar_device *cb;
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|
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@ -50,11 +59,22 @@ static inline void crossbar_writeb(int irq_no, int cb_no)
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writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
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}
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static inline int get_prev_map_irq(int cb_no)
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{
|
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int i;
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|
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for (i = cb->int_max - 1; i >= 0; i--)
|
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if (cb->irq_map[i] == cb_no)
|
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return i;
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|
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return -ENODEV;
|
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}
|
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|
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static inline int allocate_free_irq(int cb_no)
|
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{
|
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int i;
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|
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for (i = 0; i < cb->int_max; i++) {
|
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for (i = cb->int_max - 1; i >= 0; i--) {
|
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if (cb->irq_map[i] == IRQ_FREE) {
|
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cb->irq_map[i] = cb_no;
|
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return i;
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|
|
@ -64,19 +84,47 @@ static inline int allocate_free_irq(int cb_no)
|
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return -ENODEV;
|
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}
|
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|
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static inline bool needs_crossbar_write(irq_hw_number_t hw)
|
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{
|
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int cb_no;
|
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|
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if (hw > GIC_IRQ_START) {
|
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cb_no = cb->irq_map[hw - GIC_IRQ_START];
|
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if (cb_no != IRQ_RESERVED && cb_no != IRQ_SKIP)
|
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return true;
|
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}
|
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|
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return false;
|
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}
|
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|
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static int crossbar_domain_map(struct irq_domain *d, unsigned int irq,
|
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irq_hw_number_t hw)
|
||||
{
|
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cb->write(hw - GIC_IRQ_START, cb->irq_map[hw - GIC_IRQ_START]);
|
||||
if (needs_crossbar_write(hw))
|
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cb->write(hw - GIC_IRQ_START, cb->irq_map[hw - GIC_IRQ_START]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* crossbar_domain_unmap - unmap a crossbar<->irq connection
|
||||
* @d: domain of irq to unmap
|
||||
* @irq: virq number
|
||||
*
|
||||
* We do not maintain a use count of total number of map/unmap
|
||||
* calls for a particular irq to find out if a irq can be really
|
||||
* unmapped. This is because unmap is called during irq_dispose_mapping(irq),
|
||||
* after which irq is anyways unusable. So an explicit map has to be called
|
||||
* after that.
|
||||
*/
|
||||
static void crossbar_domain_unmap(struct irq_domain *d, unsigned int irq)
|
||||
{
|
||||
irq_hw_number_t hw = irq_get_irq_data(irq)->hwirq;
|
||||
|
||||
if (hw > GIC_IRQ_START)
|
||||
if (needs_crossbar_write(hw)) {
|
||||
cb->irq_map[hw - GIC_IRQ_START] = IRQ_FREE;
|
||||
cb->write(hw - GIC_IRQ_START, cb->safe_map);
|
||||
}
|
||||
}
|
||||
|
||||
static int crossbar_domain_xlate(struct irq_domain *d,
|
||||
|
|
@ -85,18 +133,41 @@ static int crossbar_domain_xlate(struct irq_domain *d,
|
|||
unsigned long *out_hwirq,
|
||||
unsigned int *out_type)
|
||||
{
|
||||
unsigned long ret;
|
||||
int ret;
|
||||
int req_num = intspec[1];
|
||||
int direct_map_num;
|
||||
|
||||
ret = allocate_free_irq(intspec[1]);
|
||||
if (req_num >= cb->max_crossbar_sources) {
|
||||
direct_map_num = req_num - cb->max_crossbar_sources;
|
||||
if (direct_map_num < cb->int_max) {
|
||||
ret = cb->irq_map[direct_map_num];
|
||||
if (ret == IRQ_RESERVED || ret == IRQ_SKIP) {
|
||||
/* We use the interrupt num as h/w irq num */
|
||||
ret = direct_map_num;
|
||||
goto found;
|
||||
}
|
||||
}
|
||||
|
||||
if (IS_ERR_VALUE(ret))
|
||||
pr_err("%s: requested crossbar number %d > max %d\n",
|
||||
__func__, req_num, cb->max_crossbar_sources);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = get_prev_map_irq(req_num);
|
||||
if (ret >= 0)
|
||||
goto found;
|
||||
|
||||
ret = allocate_free_irq(req_num);
|
||||
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
found:
|
||||
*out_hwirq = ret + GIC_IRQ_START;
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct irq_domain_ops routable_irq_domain_ops = {
|
||||
static const struct irq_domain_ops routable_irq_domain_ops = {
|
||||
.map = crossbar_domain_map,
|
||||
.unmap = crossbar_domain_unmap,
|
||||
.xlate = crossbar_domain_xlate
|
||||
|
|
@ -104,22 +175,36 @@ const struct irq_domain_ops routable_irq_domain_ops = {
|
|||
|
||||
static int __init crossbar_of_init(struct device_node *node)
|
||||
{
|
||||
int i, size, max, reserved = 0, entry;
|
||||
int i, size, max = 0, reserved = 0, entry;
|
||||
const __be32 *irqsr;
|
||||
int ret = -ENOMEM;
|
||||
|
||||
cb = kzalloc(sizeof(*cb), GFP_KERNEL);
|
||||
|
||||
if (!cb)
|
||||
return -ENOMEM;
|
||||
return ret;
|
||||
|
||||
cb->crossbar_base = of_iomap(node, 0);
|
||||
if (!cb->crossbar_base)
|
||||
goto err1;
|
||||
goto err_cb;
|
||||
|
||||
of_property_read_u32(node, "ti,max-crossbar-sources",
|
||||
&cb->max_crossbar_sources);
|
||||
if (!cb->max_crossbar_sources) {
|
||||
pr_err("missing 'ti,max-crossbar-sources' property\n");
|
||||
ret = -EINVAL;
|
||||
goto err_base;
|
||||
}
|
||||
|
||||
of_property_read_u32(node, "ti,max-irqs", &max);
|
||||
cb->irq_map = kzalloc(max * sizeof(int), GFP_KERNEL);
|
||||
if (!max) {
|
||||
pr_err("missing 'ti,max-irqs' property\n");
|
||||
ret = -EINVAL;
|
||||
goto err_base;
|
||||
}
|
||||
cb->irq_map = kcalloc(max, sizeof(int), GFP_KERNEL);
|
||||
if (!cb->irq_map)
|
||||
goto err2;
|
||||
goto err_base;
|
||||
|
||||
cb->int_max = max;
|
||||
|
||||
|
|
@ -137,15 +222,35 @@ static int __init crossbar_of_init(struct device_node *node)
|
|||
i, &entry);
|
||||
if (entry > max) {
|
||||
pr_err("Invalid reserved entry\n");
|
||||
goto err3;
|
||||
ret = -EINVAL;
|
||||
goto err_irq_map;
|
||||
}
|
||||
cb->irq_map[entry] = 0;
|
||||
cb->irq_map[entry] = IRQ_RESERVED;
|
||||
}
|
||||
}
|
||||
|
||||
cb->register_offsets = kzalloc(max * sizeof(int), GFP_KERNEL);
|
||||
/* Skip irqs hardwired to bypass the crossbar */
|
||||
irqsr = of_get_property(node, "ti,irqs-skip", &size);
|
||||
if (irqsr) {
|
||||
size /= sizeof(__be32);
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
of_property_read_u32_index(node,
|
||||
"ti,irqs-skip",
|
||||
i, &entry);
|
||||
if (entry > max) {
|
||||
pr_err("Invalid skip entry\n");
|
||||
ret = -EINVAL;
|
||||
goto err_irq_map;
|
||||
}
|
||||
cb->irq_map[entry] = IRQ_SKIP;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
cb->register_offsets = kcalloc(max, sizeof(int), GFP_KERNEL);
|
||||
if (!cb->register_offsets)
|
||||
goto err3;
|
||||
goto err_irq_map;
|
||||
|
||||
of_property_read_u32(node, "ti,reg-size", &size);
|
||||
|
||||
|
|
@ -161,7 +266,8 @@ static int __init crossbar_of_init(struct device_node *node)
|
|||
break;
|
||||
default:
|
||||
pr_err("Invalid reg-size property\n");
|
||||
goto err4;
|
||||
ret = -EINVAL;
|
||||
goto err_reg_offset;
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -170,25 +276,37 @@ static int __init crossbar_of_init(struct device_node *node)
|
|||
* reserved irqs. so find and store the offsets once.
|
||||
*/
|
||||
for (i = 0; i < max; i++) {
|
||||
if (!cb->irq_map[i])
|
||||
if (cb->irq_map[i] == IRQ_RESERVED)
|
||||
continue;
|
||||
|
||||
cb->register_offsets[i] = reserved;
|
||||
reserved += size;
|
||||
}
|
||||
|
||||
of_property_read_u32(node, "ti,irqs-safe-map", &cb->safe_map);
|
||||
/* Initialize the crossbar with safe map to start with */
|
||||
for (i = 0; i < max; i++) {
|
||||
if (cb->irq_map[i] == IRQ_RESERVED ||
|
||||
cb->irq_map[i] == IRQ_SKIP)
|
||||
continue;
|
||||
|
||||
cb->write(i, cb->safe_map);
|
||||
}
|
||||
|
||||
register_routable_domain_ops(&routable_irq_domain_ops);
|
||||
return 0;
|
||||
|
||||
err4:
|
||||
err_reg_offset:
|
||||
kfree(cb->register_offsets);
|
||||
err3:
|
||||
err_irq_map:
|
||||
kfree(cb->irq_map);
|
||||
err2:
|
||||
err_base:
|
||||
iounmap(cb->crossbar_base);
|
||||
err1:
|
||||
err_cb:
|
||||
kfree(cb);
|
||||
return -ENOMEM;
|
||||
|
||||
cb = NULL;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct of_device_id crossbar_match[] __initconst = {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,182 @@
|
|||
/*
|
||||
* Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
|
||||
* Copyright (C) 2014 Stefan Kristansson <stefan.kristiansson@saunalahti.fi>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/irq.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include "irqchip.h"
|
||||
|
||||
/* OR1K PIC implementation */
|
||||
|
||||
struct or1k_pic_dev {
|
||||
struct irq_chip chip;
|
||||
irq_flow_handler_t handle;
|
||||
unsigned long flags;
|
||||
};
|
||||
|
||||
/*
|
||||
* We're a couple of cycles faster than the generic implementations with
|
||||
* these 'fast' versions.
|
||||
*/
|
||||
|
||||
static void or1k_pic_mask(struct irq_data *data)
|
||||
{
|
||||
mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));
|
||||
}
|
||||
|
||||
static void or1k_pic_unmask(struct irq_data *data)
|
||||
{
|
||||
mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (1UL << data->hwirq));
|
||||
}
|
||||
|
||||
static void or1k_pic_ack(struct irq_data *data)
|
||||
{
|
||||
mtspr(SPR_PICSR, (1UL << data->hwirq));
|
||||
}
|
||||
|
||||
static void or1k_pic_mask_ack(struct irq_data *data)
|
||||
{
|
||||
mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));
|
||||
mtspr(SPR_PICSR, (1UL << data->hwirq));
|
||||
}
|
||||
|
||||
/*
|
||||
* There are two oddities with the OR1200 PIC implementation:
|
||||
* i) LEVEL-triggered interrupts are latched and need to be cleared
|
||||
* ii) the interrupt latch is cleared by writing a 0 to the bit,
|
||||
* as opposed to a 1 as mandated by the spec
|
||||
*/
|
||||
static void or1k_pic_or1200_ack(struct irq_data *data)
|
||||
{
|
||||
mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq));
|
||||
}
|
||||
|
||||
static void or1k_pic_or1200_mask_ack(struct irq_data *data)
|
||||
{
|
||||
mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));
|
||||
mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq));
|
||||
}
|
||||
|
||||
static struct or1k_pic_dev or1k_pic_level = {
|
||||
.chip = {
|
||||
.name = "or1k-PIC-level",
|
||||
.irq_unmask = or1k_pic_unmask,
|
||||
.irq_mask = or1k_pic_mask,
|
||||
.irq_mask_ack = or1k_pic_mask,
|
||||
},
|
||||
.handle = handle_level_irq,
|
||||
.flags = IRQ_LEVEL | IRQ_NOPROBE,
|
||||
};
|
||||
|
||||
static struct or1k_pic_dev or1k_pic_edge = {
|
||||
.chip = {
|
||||
.name = "or1k-PIC-edge",
|
||||
.irq_unmask = or1k_pic_unmask,
|
||||
.irq_mask = or1k_pic_mask,
|
||||
.irq_ack = or1k_pic_ack,
|
||||
.irq_mask_ack = or1k_pic_mask_ack,
|
||||
},
|
||||
.handle = handle_edge_irq,
|
||||
.flags = IRQ_LEVEL | IRQ_NOPROBE,
|
||||
};
|
||||
|
||||
static struct or1k_pic_dev or1k_pic_or1200 = {
|
||||
.chip = {
|
||||
.name = "or1200-PIC",
|
||||
.irq_unmask = or1k_pic_unmask,
|
||||
.irq_mask = or1k_pic_mask,
|
||||
.irq_ack = or1k_pic_or1200_ack,
|
||||
.irq_mask_ack = or1k_pic_or1200_mask_ack,
|
||||
},
|
||||
.handle = handle_level_irq,
|
||||
.flags = IRQ_LEVEL | IRQ_NOPROBE,
|
||||
};
|
||||
|
||||
static struct irq_domain *root_domain;
|
||||
|
||||
static inline int pic_get_irq(int first)
|
||||
{
|
||||
int hwirq;
|
||||
|
||||
hwirq = ffs(mfspr(SPR_PICSR) >> first);
|
||||
if (!hwirq)
|
||||
return NO_IRQ;
|
||||
else
|
||||
hwirq = hwirq + first - 1;
|
||||
|
||||
return irq_find_mapping(root_domain, hwirq);
|
||||
}
|
||||
|
||||
static void or1k_pic_handle_irq(struct pt_regs *regs)
|
||||
{
|
||||
int irq = -1;
|
||||
|
||||
while ((irq = pic_get_irq(irq + 1)) != NO_IRQ)
|
||||
handle_IRQ(irq, regs);
|
||||
}
|
||||
|
||||
static int or1k_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
|
||||
{
|
||||
struct or1k_pic_dev *pic = d->host_data;
|
||||
|
||||
irq_set_chip_and_handler(irq, &pic->chip, pic->handle);
|
||||
irq_set_status_flags(irq, pic->flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops or1k_irq_domain_ops = {
|
||||
.xlate = irq_domain_xlate_onecell,
|
||||
.map = or1k_map,
|
||||
};
|
||||
|
||||
/*
|
||||
* This sets up the IRQ domain for the PIC built in to the OpenRISC
|
||||
* 1000 CPU. This is the "root" domain as these are the interrupts
|
||||
* that directly trigger an exception in the CPU.
|
||||
*/
|
||||
static int __init or1k_pic_init(struct device_node *node,
|
||||
struct or1k_pic_dev *pic)
|
||||
{
|
||||
/* Disable all interrupts until explicitly requested */
|
||||
mtspr(SPR_PICMR, (0UL));
|
||||
|
||||
root_domain = irq_domain_add_linear(node, 32, &or1k_irq_domain_ops,
|
||||
pic);
|
||||
|
||||
set_handle_irq(or1k_pic_handle_irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init or1k_pic_or1200_init(struct device_node *node,
|
||||
struct device_node *parent)
|
||||
{
|
||||
return or1k_pic_init(node, &or1k_pic_or1200);
|
||||
}
|
||||
IRQCHIP_DECLARE(or1k_pic_or1200, "opencores,or1200-pic", or1k_pic_or1200_init);
|
||||
IRQCHIP_DECLARE(or1k_pic, "opencores,or1k-pic", or1k_pic_or1200_init);
|
||||
|
||||
static int __init or1k_pic_level_init(struct device_node *node,
|
||||
struct device_node *parent)
|
||||
{
|
||||
return or1k_pic_init(node, &or1k_pic_level);
|
||||
}
|
||||
IRQCHIP_DECLARE(or1k_pic_level, "opencores,or1k-pic-level",
|
||||
or1k_pic_level_init);
|
||||
|
||||
static int __init or1k_pic_edge_init(struct device_node *node,
|
||||
struct device_node *parent)
|
||||
{
|
||||
return or1k_pic_init(node, &or1k_pic_edge);
|
||||
}
|
||||
IRQCHIP_DECLARE(or1k_pic_edge, "opencores,or1k-pic-edge", or1k_pic_edge_init);
|
||||
Loading…
Reference in New Issue