net: stmmac: enable/disable dma irq prepared for multiple queues
This patch prepares the DMA IRQ enable/disable process for multiple queues. Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
6deee2221e
commit
4f513ecd2f
|
@ -431,8 +431,8 @@ struct stmmac_dma_ops {
|
|||
void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
|
||||
void __iomem *ioaddr);
|
||||
void (*enable_dma_transmission) (void __iomem *ioaddr);
|
||||
void (*enable_dma_irq) (void __iomem *ioaddr);
|
||||
void (*disable_dma_irq) (void __iomem *ioaddr);
|
||||
void (*enable_dma_irq)(void __iomem *ioaddr, u32 chan);
|
||||
void (*disable_dma_irq)(void __iomem *ioaddr, u32 chan);
|
||||
void (*start_tx) (void __iomem *ioaddr);
|
||||
void (*stop_tx) (void __iomem *ioaddr);
|
||||
void (*start_rx) (void __iomem *ioaddr);
|
||||
|
|
|
@ -185,9 +185,9 @@
|
|||
|
||||
int dwmac4_dma_reset(void __iomem *ioaddr);
|
||||
void dwmac4_enable_dma_transmission(void __iomem *ioaddr, u32 tail_ptr);
|
||||
void dwmac4_enable_dma_irq(void __iomem *ioaddr);
|
||||
void dwmac410_enable_dma_irq(void __iomem *ioaddr);
|
||||
void dwmac4_disable_dma_irq(void __iomem *ioaddr);
|
||||
void dwmac4_enable_dma_irq(void __iomem *ioaddr, u32 chan);
|
||||
void dwmac410_enable_dma_irq(void __iomem *ioaddr, u32 chan);
|
||||
void dwmac4_disable_dma_irq(void __iomem *ioaddr, u32 chan);
|
||||
void dwmac4_dma_start_tx(void __iomem *ioaddr);
|
||||
void dwmac4_dma_stop_tx(void __iomem *ioaddr);
|
||||
void dwmac4_dma_start_rx(void __iomem *ioaddr);
|
||||
|
|
|
@ -104,21 +104,21 @@ void dwmac4_set_rx_ring_len(void __iomem *ioaddr, u32 len)
|
|||
writel(len, ioaddr + DMA_CHAN_RX_RING_LEN(STMMAC_CHAN0));
|
||||
}
|
||||
|
||||
void dwmac4_enable_dma_irq(void __iomem *ioaddr)
|
||||
void dwmac4_enable_dma_irq(void __iomem *ioaddr, u32 chan)
|
||||
{
|
||||
writel(DMA_CHAN_INTR_DEFAULT_MASK, ioaddr +
|
||||
DMA_CHAN_INTR_ENA(STMMAC_CHAN0));
|
||||
DMA_CHAN_INTR_ENA(chan));
|
||||
}
|
||||
|
||||
void dwmac410_enable_dma_irq(void __iomem *ioaddr)
|
||||
void dwmac410_enable_dma_irq(void __iomem *ioaddr, u32 chan)
|
||||
{
|
||||
writel(DMA_CHAN_INTR_DEFAULT_MASK_4_10,
|
||||
ioaddr + DMA_CHAN_INTR_ENA(STMMAC_CHAN0));
|
||||
ioaddr + DMA_CHAN_INTR_ENA(chan));
|
||||
}
|
||||
|
||||
void dwmac4_disable_dma_irq(void __iomem *ioaddr)
|
||||
void dwmac4_disable_dma_irq(void __iomem *ioaddr, u32 chan)
|
||||
{
|
||||
writel(0, ioaddr + DMA_CHAN_INTR_ENA(STMMAC_CHAN0));
|
||||
writel(0, ioaddr + DMA_CHAN_INTR_ENA(chan));
|
||||
}
|
||||
|
||||
int dwmac4_dma_interrupt(void __iomem *ioaddr,
|
||||
|
|
|
@ -137,8 +137,8 @@
|
|||
#define DMA_CONTROL_FTF 0x00100000 /* Flush transmit FIFO */
|
||||
|
||||
void dwmac_enable_dma_transmission(void __iomem *ioaddr);
|
||||
void dwmac_enable_dma_irq(void __iomem *ioaddr);
|
||||
void dwmac_disable_dma_irq(void __iomem *ioaddr);
|
||||
void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan);
|
||||
void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan);
|
||||
void dwmac_dma_start_tx(void __iomem *ioaddr);
|
||||
void dwmac_dma_stop_tx(void __iomem *ioaddr);
|
||||
void dwmac_dma_start_rx(void __iomem *ioaddr);
|
||||
|
|
|
@ -47,12 +47,12 @@ void dwmac_enable_dma_transmission(void __iomem *ioaddr)
|
|||
writel(1, ioaddr + DMA_XMT_POLL_DEMAND);
|
||||
}
|
||||
|
||||
void dwmac_enable_dma_irq(void __iomem *ioaddr)
|
||||
void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan)
|
||||
{
|
||||
writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
|
||||
}
|
||||
|
||||
void dwmac_disable_dma_irq(void __iomem *ioaddr)
|
||||
void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan)
|
||||
{
|
||||
writel(0, ioaddr + DMA_INTR_ENA);
|
||||
}
|
||||
|
|
|
@ -1422,14 +1422,14 @@ static void stmmac_tx_clean(struct stmmac_priv *priv)
|
|||
netif_tx_unlock(priv->dev);
|
||||
}
|
||||
|
||||
static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
|
||||
static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv, u32 chan)
|
||||
{
|
||||
priv->hw->dma->enable_dma_irq(priv->ioaddr);
|
||||
priv->hw->dma->enable_dma_irq(priv->ioaddr, chan);
|
||||
}
|
||||
|
||||
static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
|
||||
static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv, u32 chan)
|
||||
{
|
||||
priv->hw->dma->disable_dma_irq(priv->ioaddr);
|
||||
priv->hw->dma->disable_dma_irq(priv->ioaddr, chan);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -1506,7 +1506,7 @@ static void stmmac_dma_interrupt(struct stmmac_priv *priv)
|
|||
status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
|
||||
if (likely((status & handle_rx)) || (status & handle_tx)) {
|
||||
if (likely(napi_schedule_prep(&priv->napi))) {
|
||||
stmmac_disable_dma_irq(priv);
|
||||
stmmac_disable_dma_irq(priv, chan);
|
||||
__napi_schedule(&priv->napi);
|
||||
}
|
||||
}
|
||||
|
@ -2832,6 +2832,7 @@ static int stmmac_poll(struct napi_struct *napi, int budget)
|
|||
{
|
||||
struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
|
||||
int work_done = 0;
|
||||
u32 chan = STMMAC_CHAN0;
|
||||
|
||||
priv->xstats.napi_poll++;
|
||||
stmmac_tx_clean(priv);
|
||||
|
@ -2839,7 +2840,7 @@ static int stmmac_poll(struct napi_struct *napi, int budget)
|
|||
work_done = stmmac_rx(priv, budget);
|
||||
if (work_done < budget) {
|
||||
napi_complete_done(napi, work_done);
|
||||
stmmac_enable_dma_irq(priv);
|
||||
stmmac_enable_dma_irq(priv, chan);
|
||||
}
|
||||
return work_done;
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue