UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

media: staging: davinci: remove vpfe driver 

The davinci_vpfe driver was merged into staging back in 2012 by Manjunath
Hadli from TI, with a long TODO list.

For all I can tell, since then it has only seen fixes for compile-time
issues and global cleanups, but nobody has actually worked on the items
on the TODO list.

To make things worse, the driver in its current form is incompatible with
the platform code in arch/arm/mach-davinci, i.e. the driver expects to
get its platform_data passed to the device as a 'struct vpfe_config',
but uses a differnet definition for that structure compared to what the
platform uses.

Finally, there is another driver for the same device in
drivers/media/platform/davinci/vpfe_capture.c. From all I can tell, the
staging version was originally a copy of a more featureful driver in TI's
downstream kernels. However, that kernel no longer supports dm365 after
linux-2.6.37, and the mainline version moved in a different direction.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
This commit is contained in:
Arnd Bergmann 2019-07-25 03:30:23 -04:00 committed by Mauro Carvalho Chehab
parent 757c2bf597
commit 4ee2224067
24 changed files with 0 additions and 14028 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/staging/media/Kconfig
View File

@ -22,8 +22,6 @@ if STAGING_MEDIA && MEDIA_SUPPORT
# Please keep them in alphabetic order
source "drivers/staging/media/allegro-dvt/Kconfig"
source "drivers/staging/media/davinci_vpfe/Kconfig"
source "drivers/staging/media/hantro/Kconfig"
source "drivers/staging/media/imx/Kconfig"

1
drivers/staging/media/Makefile
View File

@ -1,7 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_VIDEO_ALLEGRO_DVT) += allegro-dvt/
obj-$(CONFIG_VIDEO_IMX_MEDIA) += imx/
obj-$(CONFIG_VIDEO_DM365_VPFE) += davinci_vpfe/
obj-$(CONFIG_VIDEO_MESON_VDEC) += meson/vdec/
obj-$(CONFIG_VIDEO_OMAP4) += omap4iss/
obj-$(CONFIG_VIDEO_SUNXI) += sunxi/

13
drivers/staging/media/davinci_vpfe/Kconfig
View File

@ -1,13 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
config VIDEO_DM365_VPFE
tristate "DM365 VPFE Media Controller Capture Driver"
depends on VIDEO_V4L2
depends on (ARCH_DAVINCI_DM365 && !VIDEO_DM365_ISIF) || (COMPILE_TEST && !ARCH_OMAP1)
depends on VIDEO_V4L2_SUBDEV_API
depends on VIDEO_DAVINCI_VPBE_DISPLAY
select VIDEOBUF2_DMA_CONTIG
help
Support for DM365 VPFE based Media Controller Capture driver.
To compile this driver as a module, choose M here: the
module will be called vpfe-mc-capture.

11
drivers/staging/media/davinci_vpfe/Makefile
View File

@ -1,11 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_VIDEO_DM365_VPFE) += davinci-vfpe.o
davinci-vfpe-objs := \
dm365_isif.o dm365_ipipe_hw.o dm365_ipipe.o \
dm365_resizer.o dm365_ipipeif.o vpfe_mc_capture.o vpfe_video.o
# Allow building it with COMPILE_TEST on other archs
ifndef CONFIG_ARCH_DAVINCI
ccflags-y += -I $(srctree)/arch/arm/mach-davinci/include/
endif

38
drivers/staging/media/davinci_vpfe/TODO
View File

@ -1,38 +0,0 @@
TODO (general):
==================================
- User space interface refinement
- Controls should be used when possible rather than private ioctl
- No enums should be used
- Use of MC and V4L2 subdev APIs when applicable
- Single interface header might suffice
- Current interface forces to configure everything at once
- Get rid of the dm365_ipipe_hw.[ch] layer
- Active external sub-devices defined by link configuration; no strcmp
needed
- More generic platform data (i2c adapters)
- The driver should have no knowledge of possible external subdevs; see
struct vpfe_subdev_id
- Some of the hardware control should be refactorede
- Check proper serialisation (through mutexes and spinlocks)
- Names that are visible in kernel global namespace should have a common
prefix (or a few)
- While replacing the older driver in media folder, provide a compatibility
layer and compatibility tests that warrants (using the libv4l's LD_PRELOAD
approach) there is no regression for the users using the older driver.
- make it independent of arch-specific APIs (mach/mux.h).
Building of uImage and Applications:
==================================
As of now since the interface will undergo few changes all the include
files are present in staging itself, to build for dm365 follow below steps,
- copy vpfe.h from drivers/staging/media/davinci_vpfe/ to
include/media/davinci/ folder for building the uImage.
- copy davinci_vpfe_user.h from drivers/staging/media/davinci_vpfe/ to
include/uapi/linux/davinci_vpfe.h, and add a entry in Kbuild (required
for building application).
- copy dm365_ipipeif_user.h from drivers/staging/media/davinci_vpfe/ to
include/uapi/linux/dm365_ipipeif.h and a entry in Kbuild (required
for building application).

154
drivers/staging/media/davinci_vpfe/davinci-vpfe-mc.txt
View File

@ -1,154 +0,0 @@
Davinci Video processing Front End (VPFE) driver
Copyright (C) 2012 Texas Instruments Inc
Contacts: Manjunath Hadli <manjunath.hadli@ti.com>
Prabhakar Lad <prabhakar.lad@ti.com>
Introduction
============
This file documents the Texas Instruments Davinci Video processing Front End
(VPFE) driver located under drivers/media/platform/davinci. The original driver
exists for Davinci VPFE, which is now being changed to Media Controller
Framework.
Currently the driver has been successfully used on the following
version of Davinci:
DM365/DM368
The driver implements V4L2, Media controller and v4l2_subdev interfaces. Sensor,
lens and flash drivers using the v4l2_subdev interface in the kernel are
supported.
Split to subdevs
================
The Davinci VPFE is split into V4L2 subdevs, each of the blocks inside the VPFE
having one subdev to represent it. Each of the subdevs provide a V4L2 subdev
interface to userspace.
DAVINCI ISIF
DAVINCI IPIPEIF
DAVINCI IPIPE
DAVINCI CROP RESIZER
DAVINCI RESIZER A
DAVINCI RESIZER B
Each possible link in the VPFE is modelled by a link in the Media controller
interface. For an example program see [1].
ISIF, IPIPE, and RESIZER block IOCTLs
======================================
The Davinci Video processing Front End (VPFE) driver supports standard V4L2
IOCTLs and controls where possible and practical. Much of the functions provided
by the VPFE, however, does not fall under the standard IOCTL's.
In general, there is a private ioctl for configuring each of the blocks
containing hardware-dependent functions.
The following private IOCTLs are supported:
VIDIOC_VPFE_ISIF_[S/G]_RAW_PARAMS
VIDIOC_VPFE_IPIPE_[S/G]_CONFIG
VIDIOC_VPFE_RSZ_[S/G]_CONFIG
The parameter structures used by these ioctl's are described in
include/uapi/linux/davinci_vpfe.h.
The VIDIOC_VPFE_ISIF_S_RAW_PARAMS, VIDIOC_VPFE_IPIPE_S_CONFIG and
VIDIOC_VPFE_RSZ_S_CONFIG are used to configure, enable and disable functions in
the isif, ipipe and resizer blocks respectively. These IOCTL's control several
functions in the blocks they control. VIDIOC_VPFE_ISIF_S_RAW_PARAMS IOCTL
accepts a pointer to struct vpfe_isif_raw_config as its argument. Similarly
VIDIOC_VPFE_IPIPE_S_CONFIG accepts a pointer to struct vpfe_ipipe_config. And
VIDIOC_VPFE_RSZ_S_CONFIG accepts a pointer to struct vpfe_rsz_config as its
argument. Similarly VIDIOC_VPFE_ISIF_G_RAW_PARAMS, VIDIOC_VPFE_IPIPE_G_CONFIG
and VIDIOC_VPFE_RSZ_G_CONFIG are used to get the current configuration set in
the isif, ipipe and resizer blocks respectively.
The detailed functions of the VPFE itself related to a given VPFE block is
described in the Technical Reference Manuals (TRMs) --- see the end of the
document for those.
IPIPEIF block IOCTLs
======================================
The following private IOCTLs are supported:
VIDIOC_VPFE_IPIPEIF_[S/G]_CONFIG
The parameter structures used by these ioctl's are described in
include/uapi/linux/dm365_ipipeif.h
The VIDIOC_VPFE_IPIPEIF_S_CONFIG is used to configure the ipipeif
hardware block. The VIDIOC_VPFE_IPIPEIF_S_CONFIG and
VIDIOC_VPFE_IPIPEIF_G_CONFIG accepts a pointer to struct ipipeif_params
as its argument.
VPFE Operating Modes
==========================================
a: Continuous Modes
------------------------
1: tvp514x/tvp7002/mt9p031---> DAVINCI ISIF---> SDRAM
2: tvp514x/tvp7002/mt9p031---> DAVINCI ISIF---> DAVINCI IPIPEIF--->|
|
<--------------------<----------------<---------------------<---|
|
V
DAVINCI CROP RESIZER--->DAVINCI RESIZER [A/B]---> SDRAM
3: tvp514x/tvp7002/mt9p031---> DAVINCI ISIF---> DAVINCI IPIPEIF--->|
|
<--------------------<----------------<---------------------<---|
|
V
DAVINCI IPIPE---> DAVINCI CROP RESIZER--->DAVINCI RESIZER [A/B]---> SDRAM
a: Single Shot Modes
------------------------
1: SDRAM---> DAVINCI IPIPEIF---> DAVINCI IPIPE---> DAVINCI CROP RESIZER--->|
|
<----------------<----------------<------------------<---------------<--|
|
V
DAVINCI RESIZER [A/B]---> SDRAM
2: SDRAM---> DAVINCI IPIPEIF---> DAVINCI CROP RESIZER--->|
|
<----------------<----------------<---------------<---|
|
V
DAVINCI RESIZER [A/B]---> SDRAM
Technical reference manuals (TRMs) and other documentation
==========================================================
Davinci DM365 TRM:
<URL:http://www.ti.com/lit/ds/sprs457e/sprs457e.pdf>
Referenced MARCH 2009-REVISED JUNE 2011
Davinci DM368 TRM:
<URL:http://www.ti.com/lit/ds/sprs668c/sprs668c.pdf>
Referenced APRIL 2010-REVISED JUNE 2011
Davinci Video Processing Front End (VPFE) DM36x
<URL:http://www.ti.com/lit/ug/sprufg8c/sprufg8c.pdf>
References
==========
[1] http://git.ideasonboard.org/?p=media-ctl.git;a=summary

1287
drivers/staging/media/davinci_vpfe/davinci_vpfe_user.h
View File

File diff suppressed because it is too large Load Diff

1857
drivers/staging/media/davinci_vpfe/dm365_ipipe.c
View File

File diff suppressed because it is too large Load Diff

174
drivers/staging/media/davinci_vpfe/dm365_ipipe.h
View File

@ -1,174 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2012 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Contributors:
* Manjunath Hadli <manjunath.hadli@ti.com>
* Prabhakar Lad <prabhakar.lad@ti.com>
*/
#ifndef _DAVINCI_VPFE_DM365_IPIPE_H
#define _DAVINCI_VPFE_DM365_IPIPE_H
#include <linux/platform_device.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-subdev.h>
#include "davinci_vpfe_user.h"
#include "vpfe_video.h"
enum ipipe_noise_filter {
IPIPE_D2F_1ST = 0,
IPIPE_D2F_2ND = 1,
};
/* Used for driver storage */
struct ipipe_otfdpc_2_0 {
/* 0 - disable, 1 - enable */
unsigned char en;
/* defect detection method */
enum vpfe_ipipe_otfdpc_det_meth det_method;
/* Algorithm used. Applicable only when IPIPE_DPC_OTF_MIN_MAX2 is
* used
*/
enum vpfe_ipipe_otfdpc_alg alg;
struct vpfe_ipipe_otfdpc_2_0_cfg otfdpc_2_0;
};
struct ipipe_otfdpc_3_0 {
/* 0 - disable, 1 - enable */
unsigned char en;
/* defect detection method */
enum vpfe_ipipe_otfdpc_det_meth det_method;
/* Algorithm used. Applicable only when IPIPE_DPC_OTF_MIN_MAX2 is
* used
*/
enum vpfe_ipipe_otfdpc_alg alg;
struct vpfe_ipipe_otfdpc_3_0_cfg otfdpc_3_0;
};
/* Structure for configuring Luminance Adjustment module */
struct ipipe_lum_adj {
/* Brightness adjustments */
unsigned char brightness;
/* contrast adjustments */
unsigned char contrast;
};
enum ipipe_rgb2rgb {
IPIPE_RGB2RGB_1 = 0,
IPIPE_RGB2RGB_2 = 1,
};
struct ipipe_module_params {
__u32 flag;
struct vpfe_ipipe_input_config input_config;
struct vpfe_ipipe_lutdpc lutdpc;
struct vpfe_ipipe_otfdpc otfdpc;
struct vpfe_ipipe_nf nf1;
struct vpfe_ipipe_nf nf2;
struct vpfe_ipipe_gic gic;
struct vpfe_ipipe_wb wbal;
struct vpfe_ipipe_cfa cfa;
struct vpfe_ipipe_rgb2rgb rgb2rgb1;
struct vpfe_ipipe_rgb2rgb rgb2rgb2;
struct vpfe_ipipe_gamma gamma;
struct vpfe_ipipe_3d_lut lut;
struct vpfe_ipipe_rgb2yuv rgb2yuv;
struct vpfe_ipipe_gbce gbce;
struct vpfe_ipipe_yuv422_conv yuv422_conv;
struct vpfe_ipipe_yee yee;
struct vpfe_ipipe_car car;
struct vpfe_ipipe_cgs cgs;
struct ipipe_lum_adj lum_adj;
};
#define IPIPE_PAD_SINK 0
#define IPIPE_PAD_SOURCE 1
#define IPIPE_PADS_NUM 2
#define IPIPE_OUTPUT_NONE 0
#define IPIPE_OUTPUT_RESIZER (1 << 0)
enum ipipe_input_entity {
IPIPE_INPUT_NONE = 0,
IPIPE_INPUT_MEMORY = 1,
IPIPE_INPUT_CCDC = 2,
};
struct vpfe_ipipe_device {
struct v4l2_subdev subdev;
struct media_pad pads[IPIPE_PADS_NUM];
struct v4l2_mbus_framefmt formats[IPIPE_PADS_NUM];
enum ipipe_input_entity input;
unsigned int output;
struct v4l2_ctrl_handler ctrls;
void __iomem *base_addr;
void __iomem *isp5_base_addr;
struct ipipe_module_params config;
};
struct ipipe_module_if {
unsigned int param_offset;
unsigned int param_size;
unsigned int config_offset;
int (*set)(struct vpfe_ipipe_device *ipipe, void *param);
int (*get)(struct vpfe_ipipe_device *ipipe, void *param);
};
/* data paths */
enum ipipe_data_paths {
IPIPE_RAW2YUV,
/* Bayer RAW input to YCbCr output */
IPIPE_RAW2RAW,
/* Bayer Raw to Bayer output */
IPIPE_RAW2BOX,
/* Bayer Raw to Boxcar output */
IPIPE_YUV2YUV
/* YUV Raw to YUV Raw output */
};
#define IPIPE_COLPTN_R_Ye 0x0
#define IPIPE_COLPTN_Gr_Cy 0x1
#define IPIPE_COLPTN_Gb_G 0x2
#define IPIPE_COLPTN_B_Mg 0x3
#define COLPAT_EE_SHIFT 0
#define COLPAT_EO_SHIFT 2
#define COLPAT_OE_SHIFT 4
#define COLPAT_OO_SHIFT 6
#define ipipe_sgrbg_pattern \
(IPIPE_COLPTN_Gr_Cy << COLPAT_EE_SHIFT | \
IPIPE_COLPTN_R_Ye << COLPAT_EO_SHIFT | \
IPIPE_COLPTN_B_Mg << COLPAT_OE_SHIFT | \
IPIPE_COLPTN_Gb_G << COLPAT_OO_SHIFT)
#define ipipe_srggb_pattern \
(IPIPE_COLPTN_R_Ye << COLPAT_EE_SHIFT | \
IPIPE_COLPTN_Gr_Cy << COLPAT_EO_SHIFT | \
IPIPE_COLPTN_Gb_G << COLPAT_OE_SHIFT | \
IPIPE_COLPTN_B_Mg << COLPAT_OO_SHIFT)
int vpfe_ipipe_register_entities(struct vpfe_ipipe_device *ipipe,
struct v4l2_device *v4l2_dev);
int vpfe_ipipe_init(struct vpfe_ipipe_device *ipipe,
struct platform_device *pdev);
void vpfe_ipipe_unregister_entities(struct vpfe_ipipe_device *ipipe);
void vpfe_ipipe_cleanup(struct vpfe_ipipe_device *ipipe,
struct platform_device *pdev);
void vpfe_ipipe_enable(struct vpfe_device *vpfe_dev, int en);
#endif /* _DAVINCI_VPFE_DM365_IPIPE_H */

1038
drivers/staging/media/davinci_vpfe/dm365_ipipe_hw.c
View File

File diff suppressed because it is too large Load Diff

556
drivers/staging/media/davinci_vpfe/dm365_ipipe_hw.h
View File

@ -1,556 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2012 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Contributors:
* Manjunath Hadli <manjunath.hadli@ti.com>
* Prabhakar Lad <prabhakar.lad@ti.com>
*/
#ifndef _DAVINCI_VPFE_DM365_IPIPE_HW_H
#define _DAVINCI_VPFE_DM365_IPIPE_HW_H
#include "vpfe_mc_capture.h"
#define SET_LOW_ADDR 0x0000ffff
#define SET_HIGH_ADDR 0xffff0000
/* Below are the internal tables */
#define DPC_TB0_START_ADDR 0x8000
#define DPC_TB1_START_ADDR 0x8400
#define GAMMA_R_START_ADDR 0xa800
#define GAMMA_G_START_ADDR 0xb000
#define GAMMA_B_START_ADDR 0xb800
/* RAM table addresses for edge enhancement correction*/
#define YEE_TB_START_ADDR 0x8800
/* RAM table address for GBC LUT */
#define GBCE_TB_START_ADDR 0x9000
/* RAM table for 3D NF LUT */
#define D3L_TB0_START_ADDR 0x9800
#define D3L_TB1_START_ADDR 0x9c00
#define D3L_TB2_START_ADDR 0xa000
#define D3L_TB3_START_ADDR 0xa400
/* IPIPE Register Offsets from the base address */
#define IPIPE_SRC_EN 0x0000
#define IPIPE_SRC_MODE 0x0004
#define IPIPE_SRC_FMT 0x0008
#define IPIPE_SRC_COL 0x000c
#define IPIPE_SRC_VPS 0x0010
#define IPIPE_SRC_VSZ 0x0014
#define IPIPE_SRC_HPS 0x0018
#define IPIPE_SRC_HSZ 0x001c
#define IPIPE_SEL_SBU 0x0020
#define IPIPE_DMA_STA 0x0024
#define IPIPE_GCK_MMR 0x0028
#define IPIPE_GCK_PIX 0x002c
#define IPIPE_RESERVED0 0x0030
/* Defect Correction */
#define DPC_LUT_EN 0x0034
#define DPC_LUT_SEL 0x0038
#define DPC_LUT_ADR 0x003c
#define DPC_LUT_SIZ 0x0040
#define DPC_OTF_EN 0x0044
#define DPC_OTF_TYP 0x0048
#define DPC_OTF_2D_THR_R 0x004c
#define DPC_OTF_2D_THR_GR 0x0050
#define DPC_OTF_2D_THR_GB 0x0054
#define DPC_OTF_2D_THR_B 0x0058
#define DPC_OTF_2C_THR_R 0x005c
#define DPC_OTF_2C_THR_GR 0x0060
#define DPC_OTF_2C_THR_GB 0x0064
#define DPC_OTF_2C_THR_B 0x0068
#define DPC_OTF_3_SHF 0x006c
#define DPC_OTF_3D_THR 0x0070
#define DPC_OTF_3D_SLP 0x0074
#define DPC_OTF_3D_MIN 0x0078
#define DPC_OTF_3D_MAX 0x007c
#define DPC_OTF_3C_THR 0x0080
#define DPC_OTF_3C_SLP 0x0084
#define DPC_OTF_3C_MIN 0x0088
#define DPC_OTF_3C_MAX 0x008c
/* Lense Shading Correction */
#define LSC_VOFT 0x90
#define LSC_VA2 0x94
#define LSC_VA1 0x98
#define LSC_VS 0x9c
#define LSC_HOFT 0xa0
#define LSC_HA2 0xa4
#define LSC_HA1 0xa8
#define LSC_HS 0xac
#define LSC_GAIN_R 0xb0
#define LSC_GAIN_GR 0xb4
#define LSC_GAIN_GB 0xb8
#define LSC_GAIN_B 0xbc
#define LSC_OFT_R 0xc0
#define LSC_OFT_GR 0xc4
#define LSC_OFT_GB 0xc8
#define LSC_OFT_B 0xcc
#define LSC_SHF 0xd0
#define LSC_MAX 0xd4
/* Noise Filter 1. Ofsets from start address given */
#define D2F_1ST 0xd8
#define D2F_EN 0x0
#define D2F_TYP 0x4
#define D2F_THR 0x8
#define D2F_STR 0x28
#define D2F_SPR 0x48
#define D2F_EDG_MIN 0x68
#define D2F_EDG_MAX 0x6c
/* Noise Filter 2 */
#define D2F_2ND 0x148
/* GIC */
#define GIC_EN 0x1b8
#define GIC_TYP 0x1bc
#define GIC_GAN 0x1c0
#define GIC_NFGAN 0x1c4
#define GIC_THR 0x1c8
#define GIC_SLP 0x1cc
/* White Balance */
#define WB2_OFT_R 0x1d0
#define WB2_OFT_GR 0x1d4
#define WB2_OFT_GB 0x1d8
#define WB2_OFT_B 0x1dc
#define WB2_WGN_R 0x1e0
#define WB2_WGN_GR 0x1e4
#define WB2_WGN_GB 0x1e8
#define WB2_WGN_B 0x1ec
/* CFA interpolation */
#define CFA_MODE 0x1f0
#define CFA_2DIR_HPF_THR 0x1f4
#define CFA_2DIR_HPF_SLP 0x1f8
#define CFA_2DIR_MIX_THR 0x1fc
#define CFA_2DIR_MIX_SLP 0x200
#define CFA_2DIR_DIR_THR 0x204
#define CFA_2DIR_DIR_SLP 0x208
#define CFA_2DIR_NDWT 0x20c
#define CFA_MONO_HUE_FRA 0x210
#define CFA_MONO_EDG_THR 0x214
#define CFA_MONO_THR_MIN 0x218
#define CFA_MONO_THR_SLP 0x21c
#define CFA_MONO_SLP_MIN 0x220
#define CFA_MONO_SLP_SLP 0x224
#define CFA_MONO_LPWT 0x228
/* RGB to RGB conversiona - 1st */
#define RGB1_MUL_BASE 0x22c
/* Offsets from base */
#define RGB_MUL_RR 0x0
#define RGB_MUL_GR 0x4
#define RGB_MUL_BR 0x8
#define RGB_MUL_RG 0xc
#define RGB_MUL_GG 0x10
#define RGB_MUL_BG 0x14
#define RGB_MUL_RB 0x18
#define RGB_MUL_GB 0x1c
#define RGB_MUL_BB 0x20
#define RGB_OFT_OR 0x24
#define RGB_OFT_OG 0x28
#define RGB_OFT_OB 0x2c
/* Gamma */
#define GMM_CFG 0x25c
/* RGB to RGB conversiona - 2nd */
#define RGB2_MUL_BASE 0x260
/* 3D LUT */
#define D3LUT_EN 0x290
/* RGB to YUV(YCbCr) conversion */
#define YUV_ADJ 0x294
#define YUV_MUL_RY 0x298
#define YUV_MUL_GY 0x29c
#define YUV_MUL_BY 0x2a0
#define YUV_MUL_RCB 0x2a4
#define YUV_MUL_GCB 0x2a8
#define YUV_MUL_BCB 0x2ac
#define YUV_MUL_RCR 0x2b0
#define YUV_MUL_GCR 0x2b4
#define YUV_MUL_BCR 0x2b8
#define YUV_OFT_Y 0x2bc
#define YUV_OFT_CB 0x2c0
#define YUV_OFT_CR 0x2c4
#define YUV_PHS 0x2c8
/* Global Brightness and Contrast */
#define GBCE_EN 0x2cc
#define GBCE_TYP 0x2d0
/* Edge Enhancer */
#define YEE_EN 0x2d4
#define YEE_TYP 0x2d8
#define YEE_SHF 0x2dc
#define YEE_MUL_00 0x2e0
#define YEE_MUL_01 0x2e4
#define YEE_MUL_02 0x2e8
#define YEE_MUL_10 0x2ec
#define YEE_MUL_11 0x2f0
#define YEE_MUL_12 0x2f4
#define YEE_MUL_20 0x2f8
#define YEE_MUL_21 0x2fc
#define YEE_MUL_22 0x300
#define YEE_THR 0x304
#define YEE_E_GAN 0x308
#define YEE_E_THR1 0x30c
#define YEE_E_THR2 0x310
#define YEE_G_GAN 0x314
#define YEE_G_OFT 0x318
/* Chroma Artifact Reduction */
#define CAR_EN 0x31c
#define CAR_TYP 0x320
#define CAR_SW 0x324
#define CAR_HPF_TYP 0x328
#define CAR_HPF_SHF 0x32c
#define CAR_HPF_THR 0x330
#define CAR_GN1_GAN 0x334
#define CAR_GN1_SHF 0x338
#define CAR_GN1_MIN 0x33c
#define CAR_GN2_GAN 0x340
#define CAR_GN2_SHF 0x344
#define CAR_GN2_MIN 0x348
/* Chroma Gain Suppression */
#define CGS_EN 0x34c
#define CGS_GN1_L_THR 0x350
#define CGS_GN1_L_GAN 0x354
#define CGS_GN1_L_SHF 0x358
#define CGS_GN1_L_MIN 0x35c
#define CGS_GN1_H_THR 0x360
#define CGS_GN1_H_GAN 0x364
#define CGS_GN1_H_SHF 0x368
#define CGS_GN1_H_MIN 0x36c
#define CGS_GN2_L_THR 0x370
#define CGS_GN2_L_GAN 0x374
#define CGS_GN2_L_SHF 0x378
#define CGS_GN2_L_MIN 0x37c
/* Resizer */
#define RSZ_SRC_EN 0x0
#define RSZ_SRC_MODE 0x4
#define RSZ_SRC_FMT0 0x8
#define RSZ_SRC_FMT1 0xc
#define RSZ_SRC_VPS 0x10
#define RSZ_SRC_VSZ 0x14
#define RSZ_SRC_HPS 0x18
#define RSZ_SRC_HSZ 0x1c
#define RSZ_DMA_RZA 0x20
#define RSZ_DMA_RZB 0x24
#define RSZ_DMA_STA 0x28
#define RSZ_GCK_MMR 0x2c
#define RSZ_RESERVED0 0x30
#define RSZ_GCK_SDR 0x34
#define RSZ_IRQ_RZA 0x38
#define RSZ_IRQ_RZB 0x3c
#define RSZ_YUV_Y_MIN 0x40
#define RSZ_YUV_Y_MAX 0x44
#define RSZ_YUV_C_MIN 0x48
#define RSZ_YUV_C_MAX 0x4c
#define RSZ_YUV_PHS 0x50
#define RSZ_SEQ 0x54
/* Resizer Rescale Parameters */
#define RSZ_EN_A 0x58
#define RSZ_EN_B 0xe8
/*
* offset of the registers to be added with base register of
* either RSZ0 or RSZ1
*/
#define RSZ_MODE 0x4
#define RSZ_420 0x8
#define RSZ_I_VPS 0xc
#define RSZ_I_HPS 0x10
#define RSZ_O_VSZ 0x14
#define RSZ_O_HSZ 0x18
#define RSZ_V_PHS_Y 0x1c
#define RSZ_V_PHS_C 0x20
#define RSZ_V_DIF 0x24
#define RSZ_V_TYP 0x28
#define RSZ_V_LPF 0x2c
#define RSZ_H_PHS 0x30
#define RSZ_H_PHS_ADJ 0x34
#define RSZ_H_DIF 0x38
#define RSZ_H_TYP 0x3c
#define RSZ_H_LPF 0x40
#define RSZ_DWN_EN 0x44
#define RSZ_DWN_AV 0x48
/* Resizer RGB Conversion Parameters */
#define RSZ_RGB_EN 0x4c
#define RSZ_RGB_TYP 0x50
#define RSZ_RGB_BLD 0x54
/* Resizer External Memory Parameters */
#define RSZ_SDR_Y_BAD_H 0x58
#define RSZ_SDR_Y_BAD_L 0x5c
#define RSZ_SDR_Y_SAD_H 0x60
#define RSZ_SDR_Y_SAD_L 0x64
#define RSZ_SDR_Y_OFT 0x68
#define RSZ_SDR_Y_PTR_S 0x6c
#define RSZ_SDR_Y_PTR_E 0x70
#define RSZ_SDR_C_BAD_H 0x74
#define RSZ_SDR_C_BAD_L 0x78
#define RSZ_SDR_C_SAD_H 0x7c
#define RSZ_SDR_C_SAD_L 0x80
#define RSZ_SDR_C_OFT 0x84
#define RSZ_SDR_C_PTR_S 0x88
#define RSZ_SDR_C_PTR_E 0x8c
/* Macro for resizer */
#define RSZ_YUV_Y_MIN 0x40
#define RSZ_YUV_Y_MAX 0x44
#define RSZ_YUV_C_MIN 0x48
#define RSZ_YUV_C_MAX 0x4c
#define IPIPE_GCK_MMR_DEFAULT 1
#define IPIPE_GCK_PIX_DEFAULT 0xe
#define RSZ_GCK_MMR_DEFAULT 1
#define RSZ_GCK_SDR_DEFAULT 1
/* LUTDPC */
#define LUTDPC_TBL_256_EN 0
#define LUTDPC_INF_TBL_EN 1
#define LUT_DPC_START_ADDR 0
#define LUT_DPC_H_POS_MASK 0x1fff
#define LUT_DPC_V_POS_MASK 0x1fff
#define LUT_DPC_V_POS_SHIFT 13
#define LUT_DPC_CORR_METH_SHIFT 26
#define LUT_DPC_MAX_SIZE 256
#define LUT_DPC_SIZE_MASK 0x3ff
/* OTFDPC */
#define OTFDPC_DPC2_THR_MASK 0xfff
#define OTF_DET_METHOD_SHIFT 1
#define OTF_DPC3_0_SHF_MASK 3
#define OTF_DPC3_0_THR_SHIFT 6
#define OTF_DPC3_0_THR_MASK 0x3f
#define OTF_DPC3_0_SLP_MASK 0x3f
#define OTF_DPC3_0_DET_MASK 0xfff
#define OTF_DPC3_0_CORR_MASK 0xfff
/* NF (D2F) */
#define D2F_SPR_VAL_MASK 0x1f
#define D2F_SPR_VAL_SHIFT 0
#define D2F_SHFT_VAL_MASK 3
#define D2F_SHFT_VAL_SHIFT 5
#define D2F_SAMPLE_METH_SHIFT 7
#define D2F_APPLY_LSC_GAIN_SHIFT 8
#define D2F_USE_SPR_REG_VAL 0
#define D2F_STR_VAL_MASK 0x1f
#define D2F_THR_VAL_MASK 0x3ff
#define D2F_EDGE_DET_THR_MASK 0x7ff
/* Green Imbalance Correction */
#define GIC_TYP_SHIFT 0
#define GIC_THR_SEL_SHIFT 1
#define GIC_APPLY_LSC_GAIN_SHIFT 2
#define GIC_GAIN_MASK 0xff
#define GIC_THR_MASK 0xfff
#define GIC_SLOPE_MASK 0xfff
#define GIC_NFGAN_INT_MASK 7
#define GIC_NFGAN_DECI_MASK 0x1f
/* WB */
#define WB_OFFSET_MASK 0xfff
#define WB_GAIN_INT_MASK 0xf
#define WB_GAIN_DECI_MASK 0x1ff
/* CFA */
#define CFA_HPF_THR_2DIR_MASK 0x1fff
#define CFA_HPF_SLOPE_2DIR_MASK 0x3ff
#define CFA_HPF_MIX_THR_2DIR_MASK 0x1fff
#define CFA_HPF_MIX_SLP_2DIR_MASK 0x3ff
#define CFA_DIR_THR_2DIR_MASK 0x3ff
#define CFA_DIR_SLP_2DIR_MASK 0x7f
#define CFA_ND_WT_2DIR_MASK 0x3f
#define CFA_DAA_HUE_FRA_MASK 0x3f
#define CFA_DAA_EDG_THR_MASK 0xff
#define CFA_DAA_THR_MIN_MASK 0x3ff
#define CFA_DAA_THR_SLP_MASK 0x3ff
#define CFA_DAA_SLP_MIN_MASK 0x3ff
#define CFA_DAA_SLP_SLP_MASK 0x3ff
#define CFA_DAA_LP_WT_MASK 0x3f
/* RGB2RGB */
#define RGB2RGB_1_OFST_MASK 0x1fff
#define RGB2RGB_1_GAIN_INT_MASK 0xf
#define RGB2RGB_GAIN_DECI_MASK 0xff
#define RGB2RGB_2_OFST_MASK 0x7ff
#define RGB2RGB_2_GAIN_INT_MASK 0x7
/* Gamma */
#define GAMMA_BYPR_SHIFT 0
#define GAMMA_BYPG_SHIFT 1
#define GAMMA_BYPB_SHIFT 2
#define GAMMA_TBL_SEL_SHIFT 4
#define GAMMA_TBL_SIZE_SHIFT 5
#define GAMMA_MASK 0x3ff
#define GAMMA_SHIFT 10
/* 3D LUT */
#define D3_LUT_ENTRY_MASK 0x3ff
#define D3_LUT_ENTRY_R_SHIFT 20
#define D3_LUT_ENTRY_G_SHIFT 10
#define D3_LUT_ENTRY_B_SHIFT 0
/* Lumina adj */
#define LUM_ADJ_CONTR_SHIFT 0
#define LUM_ADJ_BRIGHT_SHIFT 8
/* RGB2YCbCr */
#define RGB2YCBCR_OFST_MASK 0x7ff
#define RGB2YCBCR_COEF_INT_MASK 0xf
#define RGB2YCBCR_COEF_DECI_MASK 0xff
/* GBCE */
#define GBCE_Y_VAL_MASK 0xff
#define GBCE_GAIN_VAL_MASK 0x3ff
#define GBCE_ENTRY_SHIFT 10
/* Edge Enhancements */
#define YEE_HALO_RED_EN_SHIFT 1
#define YEE_HPF_SHIFT_MASK 0xf
#define YEE_COEF_MASK 0x3ff
#define YEE_THR_MASK 0x3f
#define YEE_ES_GAIN_MASK 0xfff
#define YEE_ES_THR1_MASK 0xfff
#define YEE_ENTRY_SHIFT 9
#define YEE_ENTRY_MASK 0x1ff
/* CAR */
#define CAR_MF_THR 0xff
#define CAR_SW1_SHIFT 8
#define CAR_GAIN1_SHFT_MASK 7
#define CAR_GAIN_MIN_MASK 0x1ff
#define CAR_GAIN2_SHFT_MASK 0xf
#define CAR_HPF_SHIFT_MASK 3
/* CGS */
#define CAR_SHIFT_MASK 3
/* Resizer */
#define RSZ_BYPASS_SHIFT 1
#define RSZ_SRC_IMG_FMT_SHIFT 1
#define RSZ_SRC_Y_C_SEL_SHIFT 2
#define IPIPE_RSZ_VPS_MASK 0xffff
#define IPIPE_RSZ_HPS_MASK 0xffff
#define IPIPE_RSZ_VSZ_MASK 0x1fff
#define IPIPE_RSZ_HSZ_MASK 0x1fff
#define RSZ_HPS_MASK 0x1fff
#define RSZ_VPS_MASK 0x1fff
#define RSZ_O_HSZ_MASK 0x1fff
#define RSZ_O_VSZ_MASK 0x1fff
#define RSZ_V_PHS_MASK 0x3fff
#define RSZ_V_DIF_MASK 0x3fff
#define RSZA_H_FLIP_SHIFT 0
#define RSZA_V_FLIP_SHIFT 1
#define RSZB_H_FLIP_SHIFT 2
#define RSZB_V_FLIP_SHIFT 3
#define RSZ_A 0
#define RSZ_B 1
#define RSZ_CEN_SHIFT 1
#define RSZ_YEN_SHIFT 0
#define RSZ_TYP_Y_SHIFT 0
#define RSZ_TYP_C_SHIFT 1
#define RSZ_LPF_INT_MASK 0x3f
#define RSZ_LPF_INT_C_SHIFT 6
#define RSZ_H_PHS_MASK 0x3fff
#define RSZ_H_DIF_MASK 0x3fff
#define RSZ_DIFF_DOWN_THR 256
#define RSZ_DWN_SCALE_AV_SZ_V_SHIFT 3
#define RSZ_DWN_SCALE_AV_SZ_MASK 7
#define RSZ_RGB_MSK1_SHIFT 2
#define RSZ_RGB_MSK0_SHIFT 1
#define RSZ_RGB_TYP_SHIFT 0
#define RSZ_RGB_ALPHA_MASK 0xff
static inline u32 regr_ip(void __iomem *addr, u32 offset)
{
return readl(addr + offset);
}
static inline void regw_ip(void __iomem *addr, u32 val, u32 offset)
{
writel(val, addr + offset);
}
static inline u32 w_ip_table(void __iomem *addr, u32 val, u32 offset)
{
writel(val, addr + offset);
return val;
}
static inline u32 regr_rsz(void __iomem *addr, u32 offset)
{
return readl(addr + offset);
}
static inline u32 regw_rsz(void __iomem *addr, u32 val, u32 offset)
{
writel(val, addr + offset);
return val;
}
int config_ipipe_hw(struct vpfe_ipipe_device *ipipe);
int resizer_set_outaddr(void __iomem *rsz_base, struct resizer_params *params,
int resize_no, unsigned int address);
int rsz_enable(void __iomem *rsz_base, int rsz_id, int enable);
void rsz_src_enable(void __iomem *rsz_base, int enable);
void rsz_set_in_pix_format(unsigned char y_c);
int config_rsz_hw(struct vpfe_resizer_device *resizer,
struct resizer_params *config);
void ipipe_set_d2f_regs(void __iomem *base_addr, unsigned int id,
struct vpfe_ipipe_nf *noise_filter);
void ipipe_set_rgb2rgb_regs(void __iomem *base_addr, unsigned int id,
struct vpfe_ipipe_rgb2rgb *rgb);
void ipipe_set_yuv422_conv_regs(void __iomem *base_addr,
struct vpfe_ipipe_yuv422_conv *conv);
void ipipe_set_lum_adj_regs(void __iomem *base_addr,
struct ipipe_lum_adj *lum_adj);
void ipipe_set_rgb2ycbcr_regs(void __iomem *base_addr,
struct vpfe_ipipe_rgb2yuv *yuv);
void ipipe_set_lutdpc_regs(void __iomem *base_addr,
void __iomem *isp5_base_addr, struct vpfe_ipipe_lutdpc *lutdpc);
void ipipe_set_otfdpc_regs(void __iomem *base_addr,
struct vpfe_ipipe_otfdpc *otfdpc);
void ipipe_set_3d_lut_regs(void __iomem *base_addr,
void __iomem *isp5_base_addr, struct vpfe_ipipe_3d_lut *lut_3d);
void ipipe_set_gamma_regs(void __iomem *base_addr,
void __iomem *isp5_base_addr, struct vpfe_ipipe_gamma *gamma);
void ipipe_set_ee_regs(void __iomem *base_addr,
void __iomem *isp5_base_addr, struct vpfe_ipipe_yee *ee);
void ipipe_set_gbce_regs(void __iomem *base_addr,
void __iomem *isp5_base_addr, struct vpfe_ipipe_gbce *gbce);
void ipipe_set_gic_regs(void __iomem *base_addr, struct vpfe_ipipe_gic *gic);
void ipipe_set_cfa_regs(void __iomem *base_addr, struct vpfe_ipipe_cfa *cfa);
void ipipe_set_car_regs(void __iomem *base_addr, struct vpfe_ipipe_car *car);
void ipipe_set_cgs_regs(void __iomem *base_addr, struct vpfe_ipipe_cgs *cgs);
void ipipe_set_wb_regs(void __iomem *base_addr, struct vpfe_ipipe_wb *wb);
#endif /* _DAVINCI_VPFE_DM365_IPIPE_HW_H */

1070
drivers/staging/media/davinci_vpfe/dm365_ipipeif.c
View File

File diff suppressed because it is too large Load Diff

228
drivers/staging/media/davinci_vpfe/dm365_ipipeif.h
View File

@ -1,228 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2012 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Contributors:
* Manjunath Hadli <manjunath.hadli@ti.com>
* Prabhakar Lad <prabhakar.lad@ti.com>
*/
#ifndef _DAVINCI_VPFE_DM365_IPIPEIF_H
#define _DAVINCI_VPFE_DM365_IPIPEIF_H
#include <linux/platform_device.h>
#include <media/davinci/vpss.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-subdev.h>
#include "dm365_ipipeif_user.h"
#include "vpfe_video.h"
/* IPIPE base specific types */
enum ipipeif_data_shift {
IPIPEIF_BITS15_2 = 0,
IPIPEIF_BITS14_1 = 1,
IPIPEIF_BITS13_0 = 2,
IPIPEIF_BITS12_0 = 3,
IPIPEIF_BITS11_0 = 4,
IPIPEIF_BITS10_0 = 5,
IPIPEIF_BITS9_0 = 6,
};
enum ipipeif_clkdiv {
IPIPEIF_DIVIDE_HALF = 0,
IPIPEIF_DIVIDE_THIRD = 1,
IPIPEIF_DIVIDE_FOURTH = 2,
IPIPEIF_DIVIDE_FIFTH = 3,
IPIPEIF_DIVIDE_SIXTH = 4,
IPIPEIF_DIVIDE_EIGHTH = 5,
IPIPEIF_DIVIDE_SIXTEENTH = 6,
IPIPEIF_DIVIDE_THIRTY = 7,
};
enum ipipeif_pack_mode {
IPIPEIF_PACK_16_BIT = 0,
IPIPEIF_PACK_8_BIT = 1,
};
enum ipipeif_5_1_pack_mode {
IPIPEIF_5_1_PACK_16_BIT = 0,
IPIPEIF_5_1_PACK_8_BIT = 1,
IPIPEIF_5_1_PACK_8_BIT_A_LAW = 2,
IPIPEIF_5_1_PACK_12_BIT = 3
};
enum ipipeif_input_source {
IPIPEIF_CCDC = 0,
IPIPEIF_SDRAM_RAW = 1,
IPIPEIF_CCDC_DARKFM = 2,
IPIPEIF_SDRAM_YUV = 3,
};
enum ipipeif_ialaw {
IPIPEIF_ALAW_OFF = 0,
IPIPEIF_ALAW_ON = 1,
};
enum ipipeif_input_src1 {
IPIPEIF_SRC1_PARALLEL_PORT = 0,
IPIPEIF_SRC1_SDRAM_RAW = 1,
IPIPEIF_SRC1_ISIF_DARKFM = 2,
IPIPEIF_SRC1_SDRAM_YUV = 3,
};
enum ipipeif_dfs_dir {
IPIPEIF_PORT_MINUS_SDRAM = 0,
IPIPEIF_SDRAM_MINUS_PORT = 1,
};
enum ipipeif_chroma_phase {
IPIPEIF_CBCR_Y = 0,
IPIPEIF_Y_CBCR = 1,
};
enum ipipeif_dpcm_type {
IPIPEIF_DPCM_8BIT_10BIT = 0,
IPIPEIF_DPCM_8BIT_12BIT = 1,
};
/* data shift for IPIPE 5.1 */
enum ipipeif_5_1_data_shift {
IPIPEIF_5_1_BITS11_0 = 0,
IPIPEIF_5_1_BITS10_0 = 1,
IPIPEIF_5_1_BITS9_0 = 2,
IPIPEIF_5_1_BITS8_0 = 3,
IPIPEIF_5_1_BITS7_0 = 4,
IPIPEIF_5_1_BITS15_4 = 5,
};
#define IPIPEIF_PAD_SINK 0
#define IPIPEIF_PAD_SOURCE 1
#define IPIPEIF_NUM_PADS 2
enum ipipeif_input_entity {
IPIPEIF_INPUT_NONE = 0,
IPIPEIF_INPUT_ISIF = 1,
IPIPEIF_INPUT_MEMORY = 2,
};
enum ipipeif_output_entity {
IPIPEIF_OUTPUT_NONE = 0,
IPIPEIF_OUTPUT_IPIPE = 1,
IPIPEIF_OUTPUT_RESIZER = 2,
};
struct vpfe_ipipeif_device {
struct v4l2_subdev subdev;
struct media_pad pads[IPIPEIF_NUM_PADS];
struct v4l2_mbus_framefmt formats[IPIPEIF_NUM_PADS];
enum ipipeif_input_entity input;
unsigned int output;
struct vpfe_video_device video_in;
struct v4l2_ctrl_handler ctrls;
void __iomem *ipipeif_base_addr;
struct ipipeif_params config;
int dpcm_predictor;
int gain;
};
/* IPIPEIF Register Offsets from the base address */
#define IPIPEIF_ENABLE 0x00
#define IPIPEIF_CFG1 0x04
#define IPIPEIF_PPLN 0x08
#define IPIPEIF_LPFR 0x0c
#define IPIPEIF_HNUM 0x10
#define IPIPEIF_VNUM 0x14
#define IPIPEIF_ADDRU 0x18
#define IPIPEIF_ADDRL 0x1c
#define IPIPEIF_ADOFS 0x20
#define IPIPEIF_RSZ 0x24
#define IPIPEIF_GAIN 0x28
/* Below registers are available only on IPIPE 5.1 */
#define IPIPEIF_DPCM 0x2c
#define IPIPEIF_CFG2 0x30
#define IPIPEIF_INIRSZ 0x34
#define IPIPEIF_OCLIP 0x38
#define IPIPEIF_DTUDF 0x3c
#define IPIPEIF_CLKDIV 0x40
#define IPIPEIF_DPC1 0x44
#define IPIPEIF_DPC2 0x48
#define IPIPEIF_DFSGVL 0x4c
#define IPIPEIF_DFSGTH 0x50
#define IPIPEIF_RSZ3A 0x54
#define IPIPEIF_INIRSZ3A 0x58
#define IPIPEIF_RSZ_MIN 16
#define IPIPEIF_RSZ_MAX 112
#define IPIPEIF_RSZ_CONST 16
#define IPIPEIF_ADOFS_LSB_MASK 0x1ff
#define IPIPEIF_ADOFS_LSB_SHIFT 5
#define IPIPEIF_ADOFS_MSB_MASK 0x200
#define IPIPEIF_ADDRU_MASK 0x7ff
#define IPIPEIF_ADDRL_SHIFT 5
#define IPIPEIF_ADDRL_MASK 0xffff
#define IPIPEIF_ADDRU_SHIFT 21
#define IPIPEIF_ADDRMSB_SHIFT 31
#define IPIPEIF_ADDRMSB_LEFT_SHIFT 10
/* CFG1 Masks and shifts */
#define ONESHOT_SHIFT 0
#define DECIM_SHIFT 1
#define INPSRC_SHIFT 2
#define CLKDIV_SHIFT 4
#define AVGFILT_SHIFT 7
#define PACK8IN_SHIFT 8
#define IALAW_SHIFT 9
#define CLKSEL_SHIFT 10
#define DATASFT_SHIFT 11
#define INPSRC1_SHIFT 14
/* DPC2 */
#define IPIPEIF_DPC2_EN_SHIFT 12
#define IPIPEIF_DPC2_THR_MASK 0xfff
/* Applicable for IPIPE 5.1 */
#define IPIPEIF_DF_GAIN_EN_SHIFT 10
#define IPIPEIF_DF_GAIN_MASK 0x3ff
#define IPIPEIF_DF_GAIN_THR_MASK 0xfff
/* DPCM */
#define IPIPEIF_DPCM_BITS_SHIFT 2
#define IPIPEIF_DPCM_PRED_SHIFT 1
/* CFG2 */
#define IPIPEIF_CFG2_HDPOL_SHIFT 1
#define IPIPEIF_CFG2_VDPOL_SHIFT 2
#define IPIPEIF_CFG2_YUV8_SHIFT 6
#define IPIPEIF_CFG2_YUV16_SHIFT 3
#define IPIPEIF_CFG2_YUV8P_SHIFT 7
/* INIRSZ */
#define IPIPEIF_INIRSZ_ALNSYNC_SHIFT 13
#define IPIPEIF_INIRSZ_MASK 0x1fff
/* CLKDIV */
#define IPIPEIF_CLKDIV_M_SHIFT 8
void vpfe_ipipeif_enable(struct vpfe_device *vpfe_dev);
void vpfe_ipipeif_ss_buffer_isr(struct vpfe_ipipeif_device *ipipeif);
int vpfe_ipipeif_decimation_enabled(struct vpfe_device *vpfe_dev);
int vpfe_ipipeif_get_rsz(struct vpfe_device *vpfe_dev);
void vpfe_ipipeif_cleanup(struct vpfe_ipipeif_device *ipipeif,
struct platform_device *pdev);
int vpfe_ipipeif_init(struct vpfe_ipipeif_device *ipipeif,
struct platform_device *pdev);
int vpfe_ipipeif_register_entities(struct vpfe_ipipeif_device *ipipeif,
struct v4l2_device *vdev);
void vpfe_ipipeif_unregister_entities(struct vpfe_ipipeif_device *ipipeif);
#endif /* _DAVINCI_VPFE_DM365_IPIPEIF_H */

90
drivers/staging/media/davinci_vpfe/dm365_ipipeif_user.h
View File

@ -1,90 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2012 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Contributors:
* Manjunath Hadli <manjunath.hadli@ti.com>
* Prabhakar Lad <prabhakar.lad@ti.com>
*/
#ifndef _DAVINCI_VPFE_DM365_IPIPEIF_USER_H
#define _DAVINCI_VPFE_DM365_IPIPEIF_USER_H
/* clockdiv for IPIPE 5.1 */
struct ipipeif_5_1_clkdiv {
unsigned char m;
unsigned char n;
};
enum ipipeif_decimation {
IPIPEIF_DECIMATION_OFF,
IPIPEIF_DECIMATION_ON
};
/* DPC at the if for IPIPE 5.1 */
struct ipipeif_dpc {
/* 0 - disable, 1 - enable */
unsigned char en;
/* threshold */
unsigned short thr;
};
enum ipipeif_clock {
IPIPEIF_PIXCEL_CLK,
IPIPEIF_SDRAM_CLK
};
enum ipipeif_avg_filter {
IPIPEIF_AVG_OFF,
IPIPEIF_AVG_ON
};
struct ipipeif_5_1 {
struct ipipeif_5_1_clkdiv clk_div;
/* Defect pixel correction */
struct ipipeif_dpc dpc;
/* clipped to this value */
unsigned short clip;
/* Align HSync and VSync to rsz_start */
unsigned char align_sync;
/* resizer start position */
unsigned int rsz_start;
/* DF gain enable */
unsigned char df_gain_en;
/* DF gain value */
unsigned short df_gain;
/* DF gain threshold value */
unsigned short df_gain_thr;
};
struct ipipeif_params {
enum ipipeif_clock clock_select;
unsigned int ppln;
unsigned int lpfr;
unsigned char rsz;
enum ipipeif_decimation decimation;
enum ipipeif_avg_filter avg_filter;
/* IPIPE 5.1 */
struct ipipeif_5_1 if_5_1;
};
/*
* Private IOCTL
* VIDIOC_VPFE_IPIPEIF_S_CONFIG: Set IPIEIF configuration
* VIDIOC_VPFE_IPIPEIF_G_CONFIG: Get IPIEIF configuration
*/
#define VIDIOC_VPFE_IPIPEIF_S_CONFIG \
_IOWR('I', BASE_VIDIOC_PRIVATE + 1, struct ipipeif_params)
#define VIDIOC_VPFE_IPIPEIF_G_CONFIG \
_IOWR('I', BASE_VIDIOC_PRIVATE + 2, struct ipipeif_params)
#endif /* _DAVINCI_VPFE_DM365_IPIPEIF_USER_H */

2097
drivers/staging/media/davinci_vpfe/dm365_isif.c
View File

File diff suppressed because it is too large Load Diff

200
drivers/staging/media/davinci_vpfe/dm365_isif.h
View File

@ -1,200 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2012 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Contributors:
* Manjunath Hadli <manjunath.hadli@ti.com>
* Prabhakar Lad <prabhakar.lad@ti.com>
*/
#ifndef _DAVINCI_VPFE_DM365_ISIF_H
#define _DAVINCI_VPFE_DM365_ISIF_H
#include <linux/platform_device.h>
#include <mach/mux.h>
#include <media/davinci/vpfe_types.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include "davinci_vpfe_user.h"
#include "dm365_isif_regs.h"
#include "vpfe_video.h"
#define ISIF_CULLING_HCAPT_ODD 0xff
#define ISIF_CULLING_HCAPT_EVEN 0xff
#define ISIF_CULLING_VCAPT 0xff
#define ISIF_CADU_BITS 0x07ff
#define ISIF_CADL_BITS 0x0ffff
enum isif_pixfmt {
ISIF_PIXFMT_RAW = 0,
ISIF_PIXFMT_YCBCR_16BIT = 1,
ISIF_PIXFMT_YCBCR_8BIT = 2,
};
enum isif_frmfmt {
ISIF_FRMFMT_PROGRESSIVE = 0,
ISIF_FRMFMT_INTERLACED = 1,
};
/* PIXEL ORDER IN MEMORY from LSB to MSB */
/* only applicable for 8-bit input mode */
enum isif_pixorder {
ISIF_PIXORDER_YCBYCR = 0,
ISIF_PIXORDER_CBYCRY = 1,
};
enum isif_buftype {
ISIF_BUFTYPE_FLD_INTERLEAVED = 0,
ISIF_BUFTYPE_FLD_SEPARATED = 1,
};
struct isif_ycbcr_config {
/* v4l2 pixel format */
unsigned long v4l2_pix_fmt;
/* isif pixel format */
enum isif_pixfmt pix_fmt;
/* isif frame format */
enum isif_frmfmt frm_fmt;
/* isif crop window */
struct v4l2_rect win;
/* field polarity */
enum vpfe_pin_pol fid_pol;
/* interface VD polarity */
enum vpfe_pin_pol vd_pol;
/* interface HD polarity */
enum vpfe_pin_pol hd_pol;
/* isif pix order. Only used for ycbcr capture */
enum isif_pixorder pix_order;
/* isif buffer type. Only used for ycbcr capture */
enum isif_buftype buf_type;
};
enum isif_cfa_pattern {
ISIF_CFA_PAT_MOSAIC = 0,
ISIF_CFA_PAT_STRIPE = 1,
};
enum isif_data_msb {
/* MSB b15 */
ISIF_BIT_MSB_15 = 0,
/* MSB b14 */
ISIF_BIT_MSB_14 = 1,
/* MSB b13 */
ISIF_BIT_MSB_13 = 2,
/* MSB b12 */
ISIF_BIT_MSB_12 = 3,
/* MSB b11 */
ISIF_BIT_MSB_11 = 4,
/* MSB b10 */
ISIF_BIT_MSB_10 = 5,
/* MSB b9 */
ISIF_BIT_MSB_9 = 6,
/* MSB b8 */
ISIF_BIT_MSB_8 = 7,
/* MSB b7 */
ISIF_BIT_MSB_7 = 8,
};
struct isif_params_raw {
/* v4l2 pixel format */
unsigned long v4l2_pix_fmt;
/* isif pixel format */
enum isif_pixfmt pix_fmt;
/* isif frame format */
enum isif_frmfmt frm_fmt;
/* video window */
struct v4l2_rect win;
/* field polarity */
enum vpfe_pin_pol fid_pol;
/* interface VD polarity */
enum vpfe_pin_pol vd_pol;
/* interface HD polarity */
enum vpfe_pin_pol hd_pol;
/* buffer type. Applicable for interlaced mode */
enum isif_buftype buf_type;
/* cfa pattern */
enum isif_cfa_pattern cfa_pat;
/* Data MSB position */
enum isif_data_msb data_msb;
/* Enable horizontal flip */
unsigned char horz_flip_en;
/* Enable image invert vertically */
unsigned char image_invert_en;
unsigned char dpcm_predictor;
struct vpfe_isif_raw_config config_params;
};
enum isif_data_pack {
ISIF_PACK_16BIT = 0,
ISIF_PACK_12BIT = 1,
ISIF_PACK_8BIT = 2,
};
struct isif_gain_values {
unsigned int cr_gain;
unsigned int cgr_gain;
unsigned int cgb_gain;
unsigned int cb_gain;
unsigned int offset;
};
struct isif_oper_config {
struct isif_ycbcr_config ycbcr;
struct isif_params_raw bayer;
enum isif_data_pack data_pack;
struct isif_gain_values isif_gain_params;
void __iomem *base_addr;
void __iomem *linear_tbl0_addr;
void __iomem *linear_tbl1_addr;
};
#define ISIF_PAD_SINK 0
#define ISIF_PAD_SOURCE 1
#define ISIF_PADS_NUM 2
enum isif_input_entity {
ISIF_INPUT_NONE = 0,
ISIF_INPUT_PARALLEL = 1,
};
#define ISIF_OUTPUT_NONE (0)
#define ISIF_OUTPUT_MEMORY (1 << 0)
#define ISIF_OUTPUT_IPIPEIF (1 << 1)
struct vpfe_isif_device {
struct v4l2_subdev subdev;
struct media_pad pads[ISIF_PADS_NUM];
struct v4l2_mbus_framefmt formats[ISIF_PADS_NUM];
enum isif_input_entity input;
unsigned int output;
struct v4l2_ctrl_handler ctrls;
struct v4l2_rect crop;
struct isif_oper_config isif_cfg;
struct vpfe_video_device video_out;
};
enum v4l2_field vpfe_isif_get_fid(struct vpfe_device *vpfe_dev);
void vpfe_isif_unregister_entities(struct vpfe_isif_device *isif);
int vpfe_isif_register_entities(struct vpfe_isif_device *isif,
struct v4l2_device *dev);
int vpfe_isif_init(struct vpfe_isif_device *isif, struct platform_device *pdev);
void vpfe_isif_cleanup(struct vpfe_isif_device *vpfe_isif,
struct platform_device *pdev);
void vpfe_isif_vidint1_isr(struct vpfe_isif_device *isif);
void vpfe_isif_buffer_isr(struct vpfe_isif_device *isif);
#endif /* _DAVINCI_VPFE_DM365_ISIF_H */

291
drivers/staging/media/davinci_vpfe/dm365_isif_regs.h
View File

@ -1,291 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2012 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Contributors:
* Manjunath Hadli <manjunath.hadli@ti.com>
* Prabhakar Lad <prabhakar.lad@ti.com>
*/
#ifndef _DAVINCI_VPFE_DM365_ISIF_REGS_H
#define _DAVINCI_VPFE_DM365_ISIF_REGS_H
/* ISIF registers relative offsets */
#define SYNCEN 0x00
#define MODESET 0x04
#define HDW 0x08
#define VDW 0x0c
#define PPLN 0x10
#define LPFR 0x14
#define SPH 0x18
#define LNH 0x1c
#define SLV0 0x20
#define SLV1 0x24
#define LNV 0x28
#define CULH 0x2c
#define CULV 0x30
#define HSIZE 0x34
#define SDOFST 0x38
#define CADU 0x3c
#define CADL 0x40
#define LINCFG0 0x44
#define LINCFG1 0x48
#define CCOLP 0x4c
#define CRGAIN 0x50
#define CGRGAIN 0x54
#define CGBGAIN 0x58
#define CBGAIN 0x5c
#define COFSTA 0x60
#define FLSHCFG0 0x64
#define FLSHCFG1 0x68
#define FLSHCFG2 0x6c
#define VDINT0 0x70
#define VDINT1 0x74
#define VDINT2 0x78
#define MISC 0x7c
#define CGAMMAWD 0x80
#define REC656IF 0x84
#define CCDCFG 0x88
/*****************************************************
* Defect Correction registers
*****************************************************/
#define DFCCTL 0x8c
#define VDFSATLV 0x90
#define DFCMEMCTL 0x94
#define DFCMEM0 0x98
#define DFCMEM1 0x9c
#define DFCMEM2 0xa0
#define DFCMEM3 0xa4
#define DFCMEM4 0xa8
/****************************************************
* Black Clamp registers
****************************************************/
#define CLAMPCFG 0xac
#define CLDCOFST 0xb0
#define CLSV 0xb4
#define CLHWIN0 0xb8
#define CLHWIN1 0xbc
#define CLHWIN2 0xc0
#define CLVRV 0xc4
#define CLVWIN0 0xc8
#define CLVWIN1 0xcc
#define CLVWIN2 0xd0
#define CLVWIN3 0xd4
/****************************************************
* Lense Shading Correction
****************************************************/
#define DATAHOFST 0xd8
#define DATAVOFST 0xdc
#define LSCHVAL 0xe0
#define LSCVVAL 0xe4
#define TWODLSCCFG 0xe8
#define TWODLSCOFST 0xec
#define TWODLSCINI 0xf0
#define TWODLSCGRBU 0xf4
#define TWODLSCGRBL 0xf8
#define TWODLSCGROF 0xfc
#define TWODLSCORBU 0x100
#define TWODLSCORBL 0x104
#define TWODLSCOROF 0x108
#define TWODLSCIRQEN 0x10c
#define TWODLSCIRQST 0x110
/****************************************************
* Data formatter
****************************************************/
#define FMTCFG 0x114
#define FMTPLEN 0x118
#define FMTSPH 0x11c
#define FMTLNH 0x120
#define FMTSLV 0x124
#define FMTLNV 0x128
#define FMTRLEN 0x12c
#define FMTHCNT 0x130
#define FMTAPTR_BASE 0x134
/* Below macro for addresses FMTAPTR0 - FMTAPTR15 */
#define FMTAPTR(i) (FMTAPTR_BASE + (i * 4))
#define FMTPGMVF0 0x174
#define FMTPGMVF1 0x178
#define FMTPGMAPU0 0x17c
#define FMTPGMAPU1 0x180
#define FMTPGMAPS0 0x184
#define FMTPGMAPS1 0x188
#define FMTPGMAPS2 0x18c
#define FMTPGMAPS3 0x190
#define FMTPGMAPS4 0x194
#define FMTPGMAPS5 0x198
#define FMTPGMAPS6 0x19c
#define FMTPGMAPS7 0x1a0
/************************************************
* Color Space Converter
************************************************/
#define CSCCTL 0x1a4
#define CSCM0 0x1a8
#define CSCM1 0x1ac
#define CSCM2 0x1b0
#define CSCM3 0x1b4
#define CSCM4 0x1b8
#define CSCM5 0x1bc
#define CSCM6 0x1c0
#define CSCM7 0x1c4
#define OBWIN0 0x1c8
#define OBWIN1 0x1cc
#define OBWIN2 0x1d0
#define OBWIN3 0x1d4
#define OBVAL0 0x1d8
#define OBVAL1 0x1dc
#define OBVAL2 0x1e0
#define OBVAL3 0x1e4
#define OBVAL4 0x1e8
#define OBVAL5 0x1ec
#define OBVAL6 0x1f0
#define OBVAL7 0x1f4
#define CLKCTL 0x1f8
/* Masks & Shifts below */
#define START_PX_HOR_MASK 0x7fff
#define NUM_PX_HOR_MASK 0x7fff
#define START_VER_ONE_MASK 0x7fff
#define START_VER_TWO_MASK 0x7fff
#define NUM_LINES_VER 0x7fff
/* gain - offset masks */
#define OFFSET_MASK 0xfff
#define GAIN_SDRAM_EN_SHIFT 12
#define GAIN_IPIPE_EN_SHIFT 13
#define GAIN_H3A_EN_SHIFT 14
#define OFST_SDRAM_EN_SHIFT 8
#define OFST_IPIPE_EN_SHIFT 9
#define OFST_H3A_EN_SHIFT 10
#define GAIN_OFFSET_EN_MASK 0x7700
/* Culling */
#define CULL_PAT_EVEN_LINE_SHIFT 8
/* CCDCFG register */
#define ISIF_YCINSWP_RAW (0x00 << 4)
#define ISIF_YCINSWP_YCBCR (0x01 << 4)
#define ISIF_CCDCFG_FIDMD_LATCH_VSYNC (0x00 << 6)
#define ISIF_CCDCFG_WENLOG_AND (0x00 << 8)
#define ISIF_CCDCFG_TRGSEL_WEN (0x00 << 9)
#define ISIF_CCDCFG_EXTRG_DISABLE (0x00 << 10)
#define ISIF_LATCH_ON_VSYNC_DISABLE (0x01 << 15)
#define ISIF_LATCH_ON_VSYNC_ENABLE (0x00 << 15)
#define ISIF_DATA_PACK_MASK 0x03
#define ISIF_PIX_ORDER_SHIFT 11
#define ISIF_PIX_ORDER_MASK 0x01
#define ISIF_BW656_ENABLE (0x01 << 5)
/* MODESET registers */
#define ISIF_VDHDOUT_INPUT (0x00 << 0)
#define ISIF_INPUT_MASK 0x03
#define ISIF_INPUT_SHIFT 12
#define ISIF_FID_POL_MASK 0x01
#define ISIF_FID_POL_SHIFT 4
#define ISIF_HD_POL_MASK 0x01
#define ISIF_HD_POL_SHIFT 3
#define ISIF_VD_POL_MASK 0x01
#define ISIF_VD_POL_SHIFT 2
#define ISIF_DATAPOL_NORMAL 0x00
#define ISIF_DATAPOL_MASK 0x01
#define ISIF_DATAPOL_SHIFT 6
#define ISIF_EXWEN_DISABLE 0x00
#define ISIF_EXWEN_MASK 0x01
#define ISIF_EXWEN_SHIFT 5
#define ISIF_FRM_FMT_MASK 0x01
#define ISIF_FRM_FMT_SHIFT 7
#define ISIF_DATASFT_MASK 0x07
#define ISIF_DATASFT_SHIFT 8
#define ISIF_LPF_SHIFT 14
#define ISIF_LPF_MASK 0x1
/* GAMMAWD registers */
#define ISIF_ALAW_GAMA_WD_MASK 0xf
#define ISIF_ALAW_GAMA_WD_SHIFT 1
#define ISIF_ALAW_ENABLE 0x01
#define ISIF_GAMMAWD_CFA_MASK 0x01
#define ISIF_GAMMAWD_CFA_SHIFT 5
/* HSIZE registers */
#define ISIF_HSIZE_FLIP_MASK 0x01
#define ISIF_HSIZE_FLIP_SHIFT 12
#define ISIF_LINEOFST_MASK 0xfff
/* MISC registers */
#define ISIF_DPCM_EN_SHIFT 12
#define ISIF_DPCM_PREDICTOR_SHIFT 13
#define ISIF_DPCM_PREDICTOR_MASK 1
/* Black clamp related */
#define ISIF_BC_DCOFFSET_MASK 0x1fff
#define ISIF_BC_MODE_COLOR_MASK 1
#define ISIF_BC_MODE_COLOR_SHIFT 4
#define ISIF_HORZ_BC_MODE_MASK 3
#define ISIF_HORZ_BC_MODE_SHIFT 1
#define ISIF_HORZ_BC_WIN_COUNT_MASK 0x1f
#define ISIF_HORZ_BC_WIN_SEL_SHIFT 5
#define ISIF_HORZ_BC_PIX_LIMIT_SHIFT 6
#define ISIF_HORZ_BC_WIN_H_SIZE_MASK 3
#define ISIF_HORZ_BC_WIN_H_SIZE_SHIFT 8
#define ISIF_HORZ_BC_WIN_V_SIZE_MASK 3
#define ISIF_HORZ_BC_WIN_V_SIZE_SHIFT 12
#define ISIF_HORZ_BC_WIN_START_H_MASK 0x1fff
#define ISIF_HORZ_BC_WIN_START_V_MASK 0x1fff
#define ISIF_VERT_BC_OB_H_SZ_MASK 7
#define ISIF_VERT_BC_RST_VAL_SEL_MASK 3
#define ISIF_VERT_BC_RST_VAL_SEL_SHIFT 4
#define ISIF_VERT_BC_LINE_AVE_COEF_SHIFT 8
#define ISIF_VERT_BC_OB_START_HORZ_MASK 0x1fff
#define ISIF_VERT_BC_OB_START_VERT_MASK 0x1fff
#define ISIF_VERT_BC_OB_VERT_SZ_MASK 0x1fff
#define ISIF_VERT_BC_RST_VAL_MASK 0xfff
#define ISIF_BC_VERT_START_SUB_V_MASK 0x1fff
/* VDFC registers */
#define ISIF_VDFC_EN_SHIFT 4
#define ISIF_VDFC_CORR_MOD_MASK 3
#define ISIF_VDFC_CORR_MOD_SHIFT 5
#define ISIF_VDFC_CORR_WHOLE_LN_SHIFT 7
#define ISIF_VDFC_LEVEL_SHFT_MASK 7
#define ISIF_VDFC_LEVEL_SHFT_SHIFT 8
#define ISIF_VDFC_SAT_LEVEL_MASK 0xfff
#define ISIF_VDFC_POS_MASK 0x1fff
#define ISIF_DFCMEMCTL_DFCMARST_SHIFT 2
/* CSC registers */
#define ISIF_CSC_COEF_INTEG_MASK 7
#define ISIF_CSC_COEF_DECIMAL_MASK 0x1f
#define ISIF_CSC_COEF_INTEG_SHIFT 5
#define ISIF_CSCM_MSB_SHIFT 8
#define ISIF_DF_CSC_SPH_MASK 0x1fff
#define ISIF_DF_CSC_LNH_MASK 0x1fff
#define ISIF_DF_CSC_SLV_MASK 0x1fff
#define ISIF_DF_CSC_LNV_MASK 0x1fff
#define ISIF_DF_NUMLINES 0x7fff
#define ISIF_DF_NUMPIX 0x1fff
/* Offsets for LSC/DFC/Gain */
#define ISIF_DATA_H_OFFSET_MASK 0x1fff
#define ISIF_DATA_V_OFFSET_MASK 0x1fff
/* Linearization */
#define ISIF_LIN_CORRSFT_MASK 7
#define ISIF_LIN_CORRSFT_SHIFT 4
#define ISIF_LIN_SCALE_FACT_INTEG_SHIFT 10
#define ISIF_LIN_SCALE_FACT_DECIMAL_MASK 0x3ff
#define ISIF_LIN_ENTRY_MASK 0x3ff
/* masks and shifts*/
#define ISIF_SYNCEN_VDHDEN_MASK (1 << 0)
#define ISIF_SYNCEN_WEN_MASK (1 << 1)
#define ISIF_SYNCEN_WEN_SHIFT 1
#endif /* _DAVINCI_VPFE_DM365_ISIF_REGS_H */

1995
drivers/staging/media/davinci_vpfe/dm365_resizer.c
View File

File diff suppressed because it is too large Load Diff

241
drivers/staging/media/davinci_vpfe/dm365_resizer.h
View File

@ -1,241 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2012 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Contributors:
* Manjunath Hadli <manjunath.hadli@ti.com>
* Prabhakar Lad <prabhakar.lad@ti.com>
*/
#ifndef _DAVINCI_VPFE_DM365_RESIZER_H
#define _DAVINCI_VPFE_DM365_RESIZER_H
enum resizer_oper_mode {
RESIZER_MODE_CONTINUOUS = 0,
RESIZER_MODE_ONE_SHOT = 1,
};
struct f_div_pass {
unsigned int o_hsz;
unsigned int i_hps;
unsigned int h_phs;
unsigned int src_hps;
unsigned int src_hsz;
};
#define MAX_PASSES 2
struct f_div_param {
unsigned char en;
unsigned int num_passes;
struct f_div_pass pass[MAX_PASSES];
};
/* Resizer Rescale Parameters*/
struct resizer_scale_param {
bool h_flip;
bool v_flip;
bool cen;
bool yen;
unsigned short i_vps;
unsigned short i_hps;
unsigned short o_vsz;
unsigned short o_hsz;
unsigned short v_phs_y;
unsigned short v_phs_c;
unsigned short v_dif;
/* resize method - Luminance */
enum vpfe_rsz_intp_t v_typ_y;
/* resize method - Chrominance */
enum vpfe_rsz_intp_t v_typ_c;
/* vertical lpf intensity - Luminance */
unsigned char v_lpf_int_y;
/* vertical lpf intensity - Chrominance */
unsigned char v_lpf_int_c;
unsigned short h_phs;
unsigned short h_dif;
/* resize method - Luminance */
enum vpfe_rsz_intp_t h_typ_y;
/* resize method - Chrominance */
enum vpfe_rsz_intp_t h_typ_c;
/* horizontal lpf intensity - Luminance */
unsigned char h_lpf_int_y;
/* horizontal lpf intensity - Chrominance */
unsigned char h_lpf_int_c;
bool dscale_en;
enum vpfe_rsz_down_scale_ave_sz h_dscale_ave_sz;
enum vpfe_rsz_down_scale_ave_sz v_dscale_ave_sz;
/* store the calculated frame division parameter */
struct f_div_param f_div;
};
enum resizer_rgb_t {
OUTPUT_32BIT,
OUTPUT_16BIT
};
enum resizer_rgb_msk_t {
NOMASK = 0,
MASKLAST2 = 1,
};
/* Resizer RGB Conversion Parameters */
struct resizer_rgb {
bool rgb_en;
enum resizer_rgb_t rgb_typ;
enum resizer_rgb_msk_t rgb_msk0;
enum resizer_rgb_msk_t rgb_msk1;
unsigned int rgb_alpha_val;
};
/* Resizer External Memory Parameters */
struct rsz_ext_mem_param {
unsigned int rsz_sdr_oft_y;
unsigned int rsz_sdr_ptr_s_y;
unsigned int rsz_sdr_ptr_e_y;
unsigned int rsz_sdr_oft_c;
unsigned int rsz_sdr_ptr_s_c;
unsigned int rsz_sdr_ptr_e_c;
/* offset to be added to buffer start when flipping for y/ycbcr */
unsigned int flip_ofst_y;
/* offset to be added to buffer start when flipping for c */
unsigned int flip_ofst_c;
/* c offset for YUV 420SP */
unsigned int c_offset;
/* User Defined Y offset for YUV 420SP or YUV420ILE data */
unsigned int user_y_ofst;
/* User Defined C offset for YUV 420SP data */
unsigned int user_c_ofst;
};
enum rsz_data_source {
IPIPE_DATA,
IPIPEIF_DATA
};
enum rsz_src_img_fmt {
RSZ_IMG_422,
RSZ_IMG_420
};
enum rsz_dpaths_bypass_t {
BYPASS_OFF = 0,
BYPASS_ON = 1,
};
struct rsz_common_params {
unsigned int vps;
unsigned int vsz;
unsigned int hps;
unsigned int hsz;
/* 420 or 422 */
enum rsz_src_img_fmt src_img_fmt;
/* Y or C when src_fmt is 420, 0 - y, 1 - c */
unsigned char y_c;
/* flip raw or ycbcr */
unsigned char raw_flip;
/* IPIPE or IPIPEIF data */
enum rsz_data_source source;
enum rsz_dpaths_bypass_t passthrough;
unsigned char yuv_y_min;
unsigned char yuv_y_max;
unsigned char yuv_c_min;
unsigned char yuv_c_max;
bool rsz_seq_crv;
enum vpfe_chr_pos out_chr_pos;
};
struct resizer_params {
enum resizer_oper_mode oper_mode;
struct rsz_common_params rsz_common;
struct resizer_scale_param rsz_rsc_param[2];
struct resizer_rgb rsz2rgb[2];
struct rsz_ext_mem_param ext_mem_param[2];
bool rsz_en[2];
struct vpfe_rsz_config_params user_config;
};
#define ENABLE 1
#define DISABLE (!ENABLE)
#define RESIZER_CROP_PAD_SINK 0
#define RESIZER_CROP_PAD_SOURCE 1
#define RESIZER_CROP_PAD_SOURCE2 2
#define RESIZER_CROP_PADS_NUM 3
enum resizer_crop_input_entity {
RESIZER_CROP_INPUT_NONE = 0,
RESIZER_CROP_INPUT_IPIPEIF = 1,
RESIZER_CROP_INPUT_IPIPE = 2,
};
enum resizer_crop_output_entity {
RESIZER_CROP_OUTPUT_NONE,
RESIZER_A,
RESIZER_B,
};
struct dm365_crop_resizer_device {
struct v4l2_subdev subdev;
struct media_pad pads[RESIZER_CROP_PADS_NUM];
struct v4l2_mbus_framefmt formats[RESIZER_CROP_PADS_NUM];
enum resizer_crop_input_entity input;
enum resizer_crop_output_entity output;
enum resizer_crop_output_entity output2;
struct vpfe_resizer_device *rsz_device;
};
#define RESIZER_PAD_SINK 0
#define RESIZER_PAD_SOURCE 1
#define RESIZER_PADS_NUM 2
enum resizer_input_entity {
RESIZER_INPUT_NONE = 0,
RESIZER_INPUT_CROP_RESIZER = 1,
};
enum resizer_output_entity {
RESIZER_OUTPUT_NONE = 0,
RESIZER_OUTPUT_MEMORY = 1,
};
struct dm365_resizer_device {
struct v4l2_subdev subdev;
struct media_pad pads[RESIZER_PADS_NUM];
struct v4l2_mbus_framefmt formats[RESIZER_PADS_NUM];
enum resizer_input_entity input;
enum resizer_output_entity output;
struct vpfe_video_device video_out;
struct vpfe_resizer_device *rsz_device;
};
struct vpfe_resizer_device {
struct dm365_crop_resizer_device crop_resizer;
struct dm365_resizer_device resizer_a;
struct dm365_resizer_device resizer_b;
struct resizer_params config;
void __iomem *base_addr;
};
int vpfe_resizer_init(struct vpfe_resizer_device *vpfe_rsz,
struct platform_device *pdev);
int vpfe_resizer_register_entities(struct vpfe_resizer_device *vpfe_rsz,
struct v4l2_device *v4l2_dev);
void vpfe_resizer_unregister_entities(struct vpfe_resizer_device *vpfe_rsz);
void vpfe_resizer_cleanup(struct vpfe_resizer_device *vpfe_rsz,
struct platform_device *pdev);
void vpfe_resizer_buffer_isr(struct vpfe_resizer_device *resizer);
void vpfe_resizer_dma_isr(struct vpfe_resizer_device *resizer);
#endif /* _DAVINCI_VPFE_DM365_RESIZER_H */

83
drivers/staging/media/davinci_vpfe/vpfe.h
View File

@ -1,83 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2012 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Contributors:
* Manjunath Hadli <manjunath.hadli@ti.com>
* Prabhakar Lad <prabhakar.lad@ti.com>
*/
#ifndef _VPFE_H
#define _VPFE_H
#ifdef __KERNEL__
#include <linux/v4l2-subdev.h>
#include <linux/clk.h>
#include <linux/i2c.h>
#include <media/davinci/vpfe_types.h>
#define CAPTURE_DRV_NAME "vpfe-capture"
struct vpfe_route {
__u32 input;
__u32 output;
};
enum vpfe_subdev_id {
VPFE_SUBDEV_TVP5146 = 1,
VPFE_SUBDEV_MT9T031 = 2,
VPFE_SUBDEV_TVP7002 = 3,
VPFE_SUBDEV_MT9P031 = 4,
};
struct vpfe_ext_subdev_info {
/* v4l2 subdev */
struct v4l2_subdev *subdev;
/* Sub device module name */
char module_name[32];
/* Sub device group id */
int grp_id;
/* Number of inputs supported */
int num_inputs;
/* inputs available at the sub device */
struct v4l2_input *inputs;
/* Sub dev routing information for each input */
struct vpfe_route *routes;
/* ccdc bus/interface configuration */
struct vpfe_hw_if_param ccdc_if_params;
/* i2c subdevice board info */
struct i2c_board_info board_info;
/* Is this a camera sub device ? */
unsigned is_camera:1;
/* check if sub dev supports routing */
unsigned can_route:1;
/* registered ? */
unsigned registered:1;
};
struct vpfe_config {
/* Number of sub devices connected to vpfe */
int num_subdevs;
/* information about each subdev */
struct vpfe_ext_subdev_info *sub_devs;
/* evm card info */
char *card_name;
/* setup function for the input path */
int (*setup_input)(enum vpfe_subdev_id id);
/* number of clocks */
int num_clocks;
/* clocks used for vpfe capture */
char *clocks[];
};
#endif
#endif

716
drivers/staging/media/davinci_vpfe/vpfe_mc_capture.c
View File

@ -1,716 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2012 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Contributors:
* Manjunath Hadli <manjunath.hadli@ti.com>
* Prabhakar Lad <prabhakar.lad@ti.com>
*
*
* Driver name : VPFE Capture driver
* VPFE Capture driver allows applications to capture and stream video
* frames on DaVinci SoCs (DM6446, DM355 etc) from a YUV source such as
* TVP5146 or Raw Bayer RGB image data from an image sensor
* such as Microns' MT9T001, MT9T031 etc.
*
* These SoCs have, in common, a Video Processing Subsystem (VPSS) that
* consists of a Video Processing Front End (VPFE) for capturing
* video/raw image data and Video Processing Back End (VPBE) for displaying
* YUV data through an in-built analog encoder or Digital LCD port. This
* driver is for capture through VPFE. A typical EVM using these SoCs have
* following high level configuration.
*
* decoder(TVP5146/ YUV/
* MT9T001) --> Raw Bayer RGB ---> MUX -> VPFE (CCDC/ISIF)
* data input | |
* V |
* SDRAM |
* V
* Image Processor
* |
* V
* SDRAM
* The data flow happens from a decoder connected to the VPFE over a
* YUV embedded (BT.656/BT.1120) or separate sync or raw bayer rgb interface
* and to the input of VPFE through an optional MUX (if more inputs are
* to be interfaced on the EVM). The input data is first passed through
* CCDC (CCD Controller, a.k.a Image Sensor Interface, ISIF). The CCDC
* does very little or no processing on YUV data and does pre-process Raw
* Bayer RGB data through modules such as Defect Pixel Correction (DFC)
* Color Space Conversion (CSC), data gain/offset etc. After this, data
* can be written to SDRAM or can be connected to the image processing
* block such as IPIPE (on DM355/DM365 only).
*
* Features supported
* - MMAP IO
* - USERPTR IO
* - Capture using TVP5146 over BT.656
* - Support for interfacing decoders using sub device model
* - Work with DM365 or DM355 or DM6446 CCDC to do Raw Bayer
* RGB/YUV data capture to SDRAM.
* - Chaining of Image Processor
* - SINGLE-SHOT mode
*/
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/slab.h>
#include "vpfe.h"
#include "vpfe_mc_capture.h"
static bool debug;
static bool interface;
module_param(interface, bool, 0444);
module_param(debug, bool, 0644);
/*
* VPFE capture can be used for capturing video such as from TVP5146 or TVP7002
* and for capture raw bayer data from camera sensors such as mt9p031. At this
* point there is problem in co-existence of mt9p031 and tvp5146 due to i2c
* address collision. So set the variable below from bootargs to do either video
* capture or camera capture.
* interface = 0 - video capture (from TVP514x or such),
* interface = 1 - Camera capture (from mt9p031 or such)
* Re-visit this when we fix the co-existence issue
*/
MODULE_PARM_DESC(interface, "interface 0-1 (default:0)");
MODULE_PARM_DESC(debug, "Debug level 0-1");
MODULE_DESCRIPTION("VPFE Video for Linux Capture Driver");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Texas Instruments");
/* map mbus_fmt to pixelformat */
void mbus_to_pix(const struct v4l2_mbus_framefmt *mbus,
struct v4l2_pix_format *pix)
{
switch (mbus->code) {
case MEDIA_BUS_FMT_UYVY8_2X8:
pix->pixelformat = V4L2_PIX_FMT_UYVY;
pix->bytesperline = pix->width * 2;
break;
case MEDIA_BUS_FMT_YUYV8_2X8:
pix->pixelformat = V4L2_PIX_FMT_YUYV;
pix->bytesperline = pix->width * 2;
break;
case MEDIA_BUS_FMT_YUYV10_1X20:
pix->pixelformat = V4L2_PIX_FMT_UYVY;
pix->bytesperline = pix->width * 2;
break;
case MEDIA_BUS_FMT_SGRBG12_1X12:
pix->pixelformat = V4L2_PIX_FMT_SBGGR16;
pix->bytesperline = pix->width * 2;
break;
case MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8:
pix->pixelformat = V4L2_PIX_FMT_SGRBG10DPCM8;
pix->bytesperline = pix->width;
break;
case MEDIA_BUS_FMT_SGRBG10_ALAW8_1X8:
pix->pixelformat = V4L2_PIX_FMT_SGRBG10ALAW8;
pix->bytesperline = pix->width;
break;
case MEDIA_BUS_FMT_YDYUYDYV8_1X16:
pix->pixelformat = V4L2_PIX_FMT_NV12;
pix->bytesperline = pix->width;
break;
case MEDIA_BUS_FMT_Y8_1X8:
pix->pixelformat = V4L2_PIX_FMT_GREY;
pix->bytesperline = pix->width;
break;
case MEDIA_BUS_FMT_UV8_1X8:
pix->pixelformat = V4L2_PIX_FMT_UV8;
pix->bytesperline = pix->width;
break;
default:
pr_err("Invalid mbus code set\n");
}
/* pitch should be 32 bytes aligned */
pix->bytesperline = ALIGN(pix->bytesperline, 32);
if (pix->pixelformat == V4L2_PIX_FMT_NV12)
pix->sizeimage = pix->bytesperline * pix->height +
((pix->bytesperline * pix->height) >> 1);
else
pix->sizeimage = pix->bytesperline * pix->height;
}
/* ISR for VINT0*/
static irqreturn_t vpfe_isr(int irq, void *dev_id)
{
struct vpfe_device *vpfe_dev = dev_id;
v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "%s\n", __func__);
vpfe_isif_buffer_isr(&vpfe_dev->vpfe_isif);
vpfe_resizer_buffer_isr(&vpfe_dev->vpfe_resizer);
return IRQ_HANDLED;
}
/* vpfe_vdint1_isr() - isr handler for VINT1 interrupt */
static irqreturn_t vpfe_vdint1_isr(int irq, void *dev_id)
{
struct vpfe_device *vpfe_dev = dev_id;
v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "%s\n", __func__);
vpfe_isif_vidint1_isr(&vpfe_dev->vpfe_isif);
return IRQ_HANDLED;
}
/* vpfe_imp_dma_isr() - ISR for ipipe dma completion */
static irqreturn_t vpfe_imp_dma_isr(int irq, void *dev_id)
{
struct vpfe_device *vpfe_dev = dev_id;
v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "%s\n", __func__);
vpfe_ipipeif_ss_buffer_isr(&vpfe_dev->vpfe_ipipeif);
vpfe_resizer_dma_isr(&vpfe_dev->vpfe_resizer);
return IRQ_HANDLED;
}
/*
* vpfe_disable_clock() - Disable clocks for vpfe capture driver
* @vpfe_dev - ptr to vpfe capture device
*
* Disables clocks defined in vpfe configuration. The function
* assumes that at least one clock is to be defined which is
* true as of now.
*/
static void vpfe_disable_clock(struct vpfe_device *vpfe_dev)
{
struct vpfe_config *vpfe_cfg = vpfe_dev->cfg;
int i;
for (i = 0; i < vpfe_cfg->num_clocks; i++) {
clk_disable_unprepare(vpfe_dev->clks[i]);
clk_put(vpfe_dev->clks[i]);
}
kzfree(vpfe_dev->clks);
v4l2_info(vpfe_dev->pdev->driver, "vpfe capture clocks disabled\n");
}
/*
* vpfe_enable_clock() - Enable clocks for vpfe capture driver
* @vpfe_dev - ptr to vpfe capture device
*
* Enables clocks defined in vpfe configuration. The function
* assumes that at least one clock is to be defined which is
* true as of now.
*/
static int vpfe_enable_clock(struct vpfe_device *vpfe_dev)
{
struct vpfe_config *vpfe_cfg = vpfe_dev->cfg;
int ret = -EFAULT;
int i;
if (!vpfe_cfg->num_clocks)
return 0;
vpfe_dev->clks = kcalloc(vpfe_cfg->num_clocks,
sizeof(*vpfe_dev->clks), GFP_KERNEL);
if (!vpfe_dev->clks)
return -ENOMEM;
for (i = 0; i < vpfe_cfg->num_clocks; i++) {
if (vpfe_cfg->clocks[i] == NULL) {
v4l2_err(vpfe_dev->pdev->driver,
"clock %s is not defined in vpfe config\n",
vpfe_cfg->clocks[i]);
goto out;
}
vpfe_dev->clks[i] =
clk_get(vpfe_dev->pdev, vpfe_cfg->clocks[i]);
if (IS_ERR(vpfe_dev->clks[i])) {
v4l2_err(vpfe_dev->pdev->driver,
"Failed to get clock %s\n",
vpfe_cfg->clocks[i]);
goto out;
}
if (clk_prepare_enable(vpfe_dev->clks[i])) {
v4l2_err(vpfe_dev->pdev->driver,
"vpfe clock %s not enabled\n",
vpfe_cfg->clocks[i]);
goto out;
}
v4l2_info(vpfe_dev->pdev->driver, "vpss clock %s enabled",
vpfe_cfg->clocks[i]);
}
return 0;
out:
for (i = 0; i < vpfe_cfg->num_clocks; i++)
if (!IS_ERR(vpfe_dev->clks[i])) {
clk_disable_unprepare(vpfe_dev->clks[i]);
clk_put(vpfe_dev->clks[i]);
}
v4l2_err(vpfe_dev->pdev->driver, "Failed to enable clocks\n");
kzfree(vpfe_dev->clks);
return ret;
}
/*
* vpfe_detach_irq() - Detach IRQs for vpfe capture driver
* @vpfe_dev - ptr to vpfe capture device
*
* Detach all IRQs defined in vpfe configuration.
*/
static void vpfe_detach_irq(struct vpfe_device *vpfe_dev)
{
free_irq(vpfe_dev->ccdc_irq0, vpfe_dev);
free_irq(vpfe_dev->ccdc_irq1, vpfe_dev);
free_irq(vpfe_dev->imp_dma_irq, vpfe_dev);
}
/*
* vpfe_attach_irq() - Attach IRQs for vpfe capture driver
* @vpfe_dev - ptr to vpfe capture device
*
* Attach all IRQs defined in vpfe configuration.
*/
static int vpfe_attach_irq(struct vpfe_device *vpfe_dev)
{
int ret;
ret = request_irq(vpfe_dev->ccdc_irq0, vpfe_isr, 0,
"vpfe_capture0", vpfe_dev);
if (ret < 0) {
v4l2_err(&vpfe_dev->v4l2_dev,
"Error: requesting VINT0 interrupt\n");
return ret;
}
ret = request_irq(vpfe_dev->ccdc_irq1, vpfe_vdint1_isr, 0,
"vpfe_capture1", vpfe_dev);
if (ret < 0) {
v4l2_err(&vpfe_dev->v4l2_dev,
"Error: requesting VINT1 interrupt\n");
free_irq(vpfe_dev->ccdc_irq0, vpfe_dev);
return ret;
}
ret = request_irq(vpfe_dev->imp_dma_irq, vpfe_imp_dma_isr,
0, "Imp_Sdram_Irq", vpfe_dev);
if (ret < 0) {
v4l2_err(&vpfe_dev->v4l2_dev,
"Error: requesting IMP IRQ interrupt\n");
free_irq(vpfe_dev->ccdc_irq1, vpfe_dev);
free_irq(vpfe_dev->ccdc_irq0, vpfe_dev);
return ret;
}
return 0;
}
/*
* register_i2c_devices() - register all i2c v4l2 subdevs
* @vpfe_dev - ptr to vpfe capture device
*
* register all i2c v4l2 subdevs
*/
static int register_i2c_devices(struct vpfe_device *vpfe_dev)
{
struct vpfe_ext_subdev_info *sdinfo;
struct vpfe_config *vpfe_cfg;
struct i2c_adapter *i2c_adap;
unsigned int num_subdevs;
int ret;
int i;
int k;
vpfe_cfg = vpfe_dev->cfg;
i2c_adap = i2c_get_adapter(1);
num_subdevs = vpfe_cfg->num_subdevs;
vpfe_dev->sd =
kcalloc(num_subdevs, sizeof(struct v4l2_subdev *),
GFP_KERNEL);
if (!vpfe_dev->sd)
return -ENOMEM;
for (i = 0, k = 0; i < num_subdevs; i++) {
sdinfo = &vpfe_cfg->sub_devs[i];
/*
* register subdevices based on interface setting. Currently
* tvp5146 and mt9p031 cannot co-exists due to i2c address
* conflicts. So only one of them is registered. Re-visit this
* once we have support for i2c switch handling in i2c driver
* framework
*/
if (interface == sdinfo->is_camera) {
/* setup input path */
if (vpfe_cfg->setup_input &&
vpfe_cfg->setup_input(sdinfo->grp_id) < 0) {
ret = -EFAULT;
v4l2_info(&vpfe_dev->v4l2_dev,
"could not setup input for %s\n",
sdinfo->module_name);
goto probe_sd_out;
}
/* Load up the subdevice */
vpfe_dev->sd[k] =
v4l2_i2c_new_subdev_board(&vpfe_dev->v4l2_dev,
i2c_adap, &sdinfo->board_info,
NULL);
if (vpfe_dev->sd[k]) {
v4l2_info(&vpfe_dev->v4l2_dev,
"v4l2 sub device %s registered\n",
sdinfo->module_name);
vpfe_dev->sd[k]->grp_id = sdinfo->grp_id;
k++;
sdinfo->registered = 1;
}
} else {
v4l2_info(&vpfe_dev->v4l2_dev,
"v4l2 sub device %s is not registered\n",
sdinfo->module_name);
}
}
vpfe_dev->num_ext_subdevs = k;
return 0;
probe_sd_out:
kzfree(vpfe_dev->sd);
return ret;
}
/*
* vpfe_register_entities() - register all v4l2 subdevs and media entities
* @vpfe_dev - ptr to vpfe capture device
*
* register all v4l2 subdevs, media entities, and creates links
* between entities
*/
static int vpfe_register_entities(struct vpfe_device *vpfe_dev)
{
unsigned int flags = 0;
int ret;
int i;
/* register i2c devices first */
ret = register_i2c_devices(vpfe_dev);
if (ret)
return ret;
/* register rest of the sub-devs */
ret = vpfe_isif_register_entities(&vpfe_dev->vpfe_isif,
&vpfe_dev->v4l2_dev);
if (ret)
return ret;
ret = vpfe_ipipeif_register_entities(&vpfe_dev->vpfe_ipipeif,
&vpfe_dev->v4l2_dev);
if (ret)
goto out_isif_register;
ret = vpfe_ipipe_register_entities(&vpfe_dev->vpfe_ipipe,
&vpfe_dev->v4l2_dev);
if (ret)
goto out_ipipeif_register;
ret = vpfe_resizer_register_entities(&vpfe_dev->vpfe_resizer,
&vpfe_dev->v4l2_dev);
if (ret)
goto out_ipipe_register;
/* create links now, starting with external(i2c) entities */
for (i = 0; i < vpfe_dev->num_ext_subdevs; i++)
/*
* if entity has no pads (ex: amplifier),
* can't establish link
*/
if (vpfe_dev->sd[i]->entity.num_pads) {
ret = media_create_pad_link(&vpfe_dev->sd[i]->entity,
0, &vpfe_dev->vpfe_isif.subdev.entity,
0, flags);
if (ret < 0)
goto out_resizer_register;
}
ret = media_create_pad_link(&vpfe_dev->vpfe_isif.subdev.entity, 1,
&vpfe_dev->vpfe_ipipeif.subdev.entity,
0, flags);
if (ret < 0)
goto out_resizer_register;
ret = media_create_pad_link(&vpfe_dev->vpfe_ipipeif.subdev.entity, 1,
&vpfe_dev->vpfe_ipipe.subdev.entity,
0, flags);
if (ret < 0)
goto out_resizer_register;
ret = media_create_pad_link(&vpfe_dev->vpfe_ipipe.subdev.entity,
1, &vpfe_dev->vpfe_resizer.crop_resizer.subdev.entity,
0, flags);
if (ret < 0)
goto out_resizer_register;
ret = media_create_pad_link(&vpfe_dev->vpfe_ipipeif.subdev.entity, 1,
&vpfe_dev->vpfe_resizer.crop_resizer.subdev.entity,
0, flags);
if (ret < 0)
goto out_resizer_register;
ret = v4l2_device_register_subdev_nodes(&vpfe_dev->v4l2_dev);
if (ret < 0)
goto out_resizer_register;
return 0;
out_resizer_register:
vpfe_resizer_unregister_entities(&vpfe_dev->vpfe_resizer);
out_ipipe_register:
vpfe_ipipe_unregister_entities(&vpfe_dev->vpfe_ipipe);
out_ipipeif_register:
vpfe_ipipeif_unregister_entities(&vpfe_dev->vpfe_ipipeif);
out_isif_register:
vpfe_isif_unregister_entities(&vpfe_dev->vpfe_isif);
return ret;
}
/*
* vpfe_unregister_entities() - unregister all v4l2 subdevs and media entities
* @vpfe_dev - ptr to vpfe capture device
*
* unregister all v4l2 subdevs and media entities
*/
static void vpfe_unregister_entities(struct vpfe_device *vpfe_dev)
{
vpfe_isif_unregister_entities(&vpfe_dev->vpfe_isif);
vpfe_ipipeif_unregister_entities(&vpfe_dev->vpfe_ipipeif);
vpfe_ipipe_unregister_entities(&vpfe_dev->vpfe_ipipe);
vpfe_resizer_unregister_entities(&vpfe_dev->vpfe_resizer);
}
/*
* vpfe_cleanup_modules() - cleanup all non-i2c v4l2 subdevs
* @vpfe_dev - ptr to vpfe capture device
* @pdev - pointer to platform device
*
* cleanup all v4l2 subdevs
*/
static void vpfe_cleanup_modules(struct vpfe_device *vpfe_dev,
struct platform_device *pdev)
{
vpfe_isif_cleanup(&vpfe_dev->vpfe_isif, pdev);
vpfe_ipipeif_cleanup(&vpfe_dev->vpfe_ipipeif, pdev);
vpfe_ipipe_cleanup(&vpfe_dev->vpfe_ipipe, pdev);
vpfe_resizer_cleanup(&vpfe_dev->vpfe_resizer, pdev);
}
/*
* vpfe_initialize_modules() - initialize all non-i2c v4l2 subdevs
* @vpfe_dev - ptr to vpfe capture device
* @pdev - pointer to platform device
*
* initialize all v4l2 subdevs and media entities
*/
static int vpfe_initialize_modules(struct vpfe_device *vpfe_dev,
struct platform_device *pdev)
{
int ret;
ret = vpfe_isif_init(&vpfe_dev->vpfe_isif, pdev);
if (ret)
return ret;
ret = vpfe_ipipeif_init(&vpfe_dev->vpfe_ipipeif, pdev);
if (ret)
goto out_isif_init;
ret = vpfe_ipipe_init(&vpfe_dev->vpfe_ipipe, pdev);
if (ret)
goto out_ipipeif_init;
ret = vpfe_resizer_init(&vpfe_dev->vpfe_resizer, pdev);
if (ret)
goto out_ipipe_init;
return 0;
out_ipipe_init:
vpfe_ipipe_cleanup(&vpfe_dev->vpfe_ipipe, pdev);
out_ipipeif_init:
vpfe_ipipeif_cleanup(&vpfe_dev->vpfe_ipipeif, pdev);
out_isif_init:
vpfe_isif_cleanup(&vpfe_dev->vpfe_isif, pdev);
return ret;
}
/*
* vpfe_probe() : vpfe probe function
* @pdev: platform device pointer
*
* This function creates device entries by register itself to the V4L2 driver
* and initializes fields of each device objects
*/
static int vpfe_probe(struct platform_device *pdev)
{
struct vpfe_device *vpfe_dev;
struct resource *res1;
int ret = -ENOMEM;
vpfe_dev = kzalloc(sizeof(*vpfe_dev), GFP_KERNEL);
if (!vpfe_dev)
return ret;
if (pdev->dev.platform_data == NULL) {
v4l2_err(pdev->dev.driver, "Unable to get vpfe config\n");
ret = -ENOENT;
goto probe_free_dev_mem;
}
vpfe_dev->cfg = pdev->dev.platform_data;
if (vpfe_dev->cfg->card_name == NULL ||
vpfe_dev->cfg->sub_devs == NULL) {
v4l2_err(pdev->dev.driver, "null ptr in vpfe_cfg\n");
ret = -ENOENT;
goto probe_free_dev_mem;
}
/* Get VINT0 irq resource */
res1 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (!res1) {
v4l2_err(pdev->dev.driver,
"Unable to get interrupt for VINT0\n");
ret = -ENOENT;
goto probe_free_dev_mem;
}
vpfe_dev->ccdc_irq0 = res1->start;
/* Get VINT1 irq resource */
res1 = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
if (!res1) {
v4l2_err(pdev->dev.driver,
"Unable to get interrupt for VINT1\n");
ret = -ENOENT;
goto probe_free_dev_mem;
}
vpfe_dev->ccdc_irq1 = res1->start;
/* Get DMA irq resource */
res1 = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
if (!res1) {
v4l2_err(pdev->dev.driver,
"Unable to get interrupt for DMA\n");
ret = -ENOENT;
goto probe_free_dev_mem;
}
vpfe_dev->imp_dma_irq = res1->start;
vpfe_dev->pdev = &pdev->dev;
/* enable vpss clocks */
ret = vpfe_enable_clock(vpfe_dev);
if (ret)
goto probe_free_dev_mem;
ret = vpfe_initialize_modules(vpfe_dev, pdev);
if (ret)
goto probe_disable_clock;
vpfe_dev->media_dev.dev = vpfe_dev->pdev;
strscpy((char *)&vpfe_dev->media_dev.model, "davinci-media",
sizeof(vpfe_dev->media_dev.model));
ret = media_device_register(&vpfe_dev->media_dev);
if (ret) {
v4l2_err(pdev->dev.driver,
"Unable to register media device.\n");
goto probe_out_entities_cleanup;
}
vpfe_dev->v4l2_dev.mdev = &vpfe_dev->media_dev;
ret = v4l2_device_register(&pdev->dev, &vpfe_dev->v4l2_dev);
if (ret) {
v4l2_err(pdev->dev.driver, "Unable to register v4l2 device.\n");
goto probe_out_media_unregister;
}
v4l2_info(&vpfe_dev->v4l2_dev, "v4l2 device registered\n");
/* set the driver data in platform device */
platform_set_drvdata(pdev, vpfe_dev);
/* register subdevs/entities */
ret = vpfe_register_entities(vpfe_dev);
if (ret)
goto probe_out_v4l2_unregister;
ret = vpfe_attach_irq(vpfe_dev);
if (ret)
goto probe_out_entities_unregister;
return 0;
probe_out_entities_unregister:
vpfe_unregister_entities(vpfe_dev);
kzfree(vpfe_dev->sd);
probe_out_v4l2_unregister:
v4l2_device_unregister(&vpfe_dev->v4l2_dev);
probe_out_media_unregister:
media_device_unregister(&vpfe_dev->media_dev);
probe_out_entities_cleanup:
vpfe_cleanup_modules(vpfe_dev, pdev);
probe_disable_clock:
vpfe_disable_clock(vpfe_dev);
probe_free_dev_mem:
kzfree(vpfe_dev);
return ret;
}
/*
* vpfe_remove : This function un-registers device from V4L2 driver
*/
static int vpfe_remove(struct platform_device *pdev)
{
struct vpfe_device *vpfe_dev = platform_get_drvdata(pdev);
v4l2_info(pdev->dev.driver, "%s\n", __func__);
kzfree(vpfe_dev->sd);
vpfe_detach_irq(vpfe_dev);
vpfe_unregister_entities(vpfe_dev);
vpfe_cleanup_modules(vpfe_dev, pdev);
v4l2_device_unregister(&vpfe_dev->v4l2_dev);
media_device_unregister(&vpfe_dev->media_dev);
vpfe_disable_clock(vpfe_dev);
kzfree(vpfe_dev);
return 0;
}
static struct platform_driver vpfe_driver = {
.driver = {
.name = CAPTURE_DRV_NAME,
},
.probe = vpfe_probe,
.remove = vpfe_remove,
};
module_platform_driver(vpfe_driver);

90
drivers/staging/media/davinci_vpfe/vpfe_mc_capture.h
View File

@ -1,90 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2012 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Contributors:
* Manjunath Hadli <manjunath.hadli@ti.com>
* Prabhakar Lad <prabhakar.lad@ti.com>
*/
#ifndef _DAVINCI_VPFE_MC_CAPTURE_H
#define _DAVINCI_VPFE_MC_CAPTURE_H
#include "dm365_ipipe.h"
#include "dm365_ipipeif.h"
#include "dm365_isif.h"
#include "dm365_resizer.h"
#include "vpfe_video.h"
#define VPFE_MAJOR_RELEASE 0
#define VPFE_MINOR_RELEASE 0
#define VPFE_BUILD 1
#define VPFE_CAPTURE_VERSION_CODE ((VPFE_MAJOR_RELEASE << 16) | \
(VPFE_MINOR_RELEASE << 8) | \
VPFE_BUILD)
/* IPIPE hardware limits */
#define IPIPE_MAX_OUTPUT_WIDTH_A 2176
#define IPIPE_MAX_OUTPUT_WIDTH_B 640
/* Based on max resolution supported. QXGA */
#define IPIPE_MAX_OUTPUT_HEIGHT_A 1536
/* Based on max resolution supported. VGA */
#define IPIPE_MAX_OUTPUT_HEIGHT_B 480
#define to_vpfe_device(ptr_module) \
container_of(ptr_module, struct vpfe_device, vpfe_##ptr_module)
#define to_device(ptr_module) \
(to_vpfe_device(ptr_module)->dev)
struct vpfe_device {
/* external registered sub devices */
struct v4l2_subdev **sd;
/* number of registered external subdevs */
unsigned int num_ext_subdevs;
/* vpfe cfg */
struct vpfe_config *cfg;
/* clock ptrs for vpfe capture */
struct clk **clks;
/* V4l2 device */
struct v4l2_device v4l2_dev;
/* parent device */
struct device *pdev;
/* IRQ number for DMA transfer completion at the image processor */
unsigned int imp_dma_irq;
/* CCDC IRQs used when CCDC/ISIF output to SDRAM */
unsigned int ccdc_irq0;
unsigned int ccdc_irq1;
/* media device */
struct media_device media_dev;
/* ccdc subdevice */
struct vpfe_isif_device vpfe_isif;
/* ipipeif subdevice */
struct vpfe_ipipeif_device vpfe_ipipeif;
/* ipipe subdevice */
struct vpfe_ipipe_device vpfe_ipipe;
/* resizer subdevice */
struct vpfe_resizer_device vpfe_resizer;
};
/* File handle structure */
struct vpfe_fh {
struct v4l2_fh vfh;
struct vpfe_video_device *video;
/* Indicates whether this file handle is doing IO */
u8 io_allowed;
};
void mbus_to_pix(const struct v4l2_mbus_framefmt *mbus,
struct v4l2_pix_format *pix);
#endif /* _DAVINCI_VPFE_MC_CAPTURE_H */

1646
drivers/staging/media/davinci_vpfe/vpfe_video.c
View File

File diff suppressed because it is too large Load Diff

150
drivers/staging/media/davinci_vpfe/vpfe_video.h
View File

@ -1,150 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2012 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Contributors:
* Manjunath Hadli <manjunath.hadli@ti.com>
* Prabhakar Lad <prabhakar.lad@ti.com>
*/
#ifndef _DAVINCI_VPFE_VIDEO_H
#define _DAVINCI_VPFE_VIDEO_H
#include <media/videobuf2-v4l2.h>
#include <media/videobuf2-dma-contig.h>
struct vpfe_device;
/*
* struct vpfe_video_operations - VPFE video operations
* @queue: Resume streaming when a buffer is queued. Called on VIDIOC_QBUF
* if there was no buffer previously queued.
*/
struct vpfe_video_operations {
int (*queue)(struct vpfe_device *vpfe_dev, unsigned long addr);
};
enum vpfe_pipeline_stream_state {
VPFE_PIPELINE_STREAM_STOPPED = 0,
VPFE_PIPELINE_STREAM_CONTINUOUS = 1,
VPFE_PIPELINE_STREAM_SINGLESHOT = 2,
};
enum vpfe_video_state {
/* indicates that buffer is not queued */
VPFE_VIDEO_BUFFER_NOT_QUEUED = 0,
/* indicates that buffer is queued */
VPFE_VIDEO_BUFFER_QUEUED = 1,
};
struct vpfe_pipeline {
/* media pipeline */
struct media_pipeline *pipe;
struct media_graph graph;
/* state of the pipeline, continuous,
* single-shot or stopped
*/
enum vpfe_pipeline_stream_state state;
/* number of active input video entities */
unsigned int input_num;
/* number of active output video entities */
unsigned int output_num;
/* input video nodes in case of single-shot mode */
struct vpfe_video_device *inputs[10];
/* capturing video nodes */
struct vpfe_video_device *outputs[10];
};
#define to_vpfe_pipeline(__e) \
container_of((__e)->pipe, struct vpfe_pipeline, pipe)
#define to_vpfe_video(vdev) \
container_of(vdev, struct vpfe_video_device, video_dev)
struct vpfe_cap_buffer {
struct vb2_v4l2_buffer vb;
struct list_head list;
};
struct vpfe_video_device {
/* vpfe device */
struct vpfe_device *vpfe_dev;
/* video dev */
struct video_device video_dev;
/* media pad of video entity */
struct media_pad pad;
/* video operations supported by video device */
const struct vpfe_video_operations *ops;
/* type of the video buffers used by user */
enum v4l2_buf_type type;
/* Indicates id of the field which is being captured */
u32 field_id;
/* pipeline for which video device is part of */
struct vpfe_pipeline pipe;
/* Indicates whether streaming started */
u8 started;
/* Indicates state of the stream */
unsigned int state;
/* current input at the sub device */
int current_input;
/*
* This field keeps track of type of buffer exchange mechanism
* user has selected
*/
enum v4l2_memory memory;
/* number of open instances of the channel */
u32 usrs;
/* flag to indicate whether decoder is initialized */
u8 initialized;
/* skip frame count */
u8 skip_frame_count;
/* skip frame count init value */
u8 skip_frame_count_init;
/* time per frame for skipping */
struct v4l2_fract timeperframe;
/* ptr to currently selected sub device */
struct vpfe_ext_subdev_info *current_ext_subdev;
/* Pointer pointing to current vpfe_cap_buffer */
struct vpfe_cap_buffer *cur_frm;
/* Pointer pointing to next vpfe_cap_buffer */
struct vpfe_cap_buffer *next_frm;
/* Used to store pixel format */
struct v4l2_format fmt;
struct vb2_queue buffer_queue;
/* Queue of filled frames */
struct list_head dma_queue;
spinlock_t irqlock;
/* IRQ lock for DMA queue */
spinlock_t dma_queue_lock;
/* lock used to serialize all video4linux ioctls */
struct mutex lock;
/* number of users performing IO */
u32 io_usrs;
/* Currently selected or default standard */
v4l2_std_id stdid;
/*
* offset where second field starts from the starting of the
* buffer for field separated YCbCr formats
*/
u32 field_off;
};
int vpfe_video_is_pipe_ready(struct vpfe_pipeline *pipe);
void vpfe_video_unregister(struct vpfe_video_device *video);
int vpfe_video_register(struct vpfe_video_device *video,
struct v4l2_device *vdev);
int vpfe_video_init(struct vpfe_video_device *video, const char *name);
void vpfe_video_process_buffer_complete(struct vpfe_video_device *video);
void vpfe_video_schedule_bottom_field(struct vpfe_video_device *video);
void vpfe_video_schedule_next_buffer(struct vpfe_video_device *video);
#endif /* _DAVINCI_VPFE_VIDEO_H */