mtd: spi-nor: Add a RWW flag
Introduce a new (no SFDP) flag for the feature that we are about to support: Read While Write. This means, if the chip has several banks and supports RWW, once a page of data to write has been transferred into the chip's internal SRAM, another read operation happening on a different bank can be performed during the tPROG delay. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20230328154105.448540-7-miquel.raynal@bootlin.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
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@ -2530,6 +2530,9 @@ static void spi_nor_init_flags(struct spi_nor *nor)
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if (flags & NO_CHIP_ERASE)
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nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
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if (flags & SPI_NOR_RWW)
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nor->flags |= SNOR_F_RWW;
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}
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/**
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@ -130,6 +130,7 @@ enum spi_nor_option_flags {
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SNOR_F_IO_MODE_EN_VOLATILE = BIT(11),
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SNOR_F_SOFT_RESET = BIT(12),
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SNOR_F_SWP_IS_VOLATILE = BIT(13),
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SNOR_F_RWW = BIT(14),
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};
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struct spi_nor_read_command {
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@ -462,6 +463,7 @@ struct spi_nor_fixups {
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* NO_CHIP_ERASE: chip does not support chip erase.
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* SPI_NOR_NO_FR: can't do fastread.
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* SPI_NOR_QUAD_PP: flash supports Quad Input Page Program.
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* SPI_NOR_RWW: flash supports reads while write.
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*
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* @no_sfdp_flags: flags that indicate support that can be discovered via SFDP.
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* Used when SFDP tables are not defined in the flash. These
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@ -513,6 +515,7 @@ struct flash_info {
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#define NO_CHIP_ERASE BIT(7)
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#define SPI_NOR_NO_FR BIT(8)
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#define SPI_NOR_QUAD_PP BIT(9)
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#define SPI_NOR_RWW BIT(10)
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u8 no_sfdp_flags;
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#define SPI_NOR_SKIP_SFDP BIT(0)
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@ -25,6 +25,7 @@ static const char *const snor_f_names[] = {
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SNOR_F_NAME(IO_MODE_EN_VOLATILE),
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SNOR_F_NAME(SOFT_RESET),
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SNOR_F_NAME(SWP_IS_VOLATILE),
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SNOR_F_NAME(RWW),
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};
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#undef SNOR_F_NAME
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