arm64/sme: Document SME 2 and SME 2.1 ABI
As well as a number of simple features which only add new instructions and require corresponding hwcaps SME2 introduces a new register ZT0 for which we must define ABI. Fortunately this is a fixed size 512 bits and therefore much more straightforward than the base SME state, the only wrinkle is that it is only accessible when ZA is accessible. While there is only a single register the architecture is written with a view to exensibility, including a number in the name, so follow this in the ABI. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20221208-arm64-sme2-v4-4-f2fa0aef982f@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Mark Brown
Catalin Marinas
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@ -18,14 +18,19 @@ model features for SME is included in Appendix A.
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1. General
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-----------
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* PSTATE.SM, PSTATE.ZA, the streaming mode vector length, the ZA
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register state and TPIDR2_EL0 are tracked per thread.
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* PSTATE.SM, PSTATE.ZA, the streaming mode vector length, the ZA and (when
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present) ZTn register state and TPIDR2_EL0 are tracked per thread.
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* The presence of SME is reported to userspace via HWCAP2_SME in the aux vector
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AT_HWCAP2 entry. Presence of this flag implies the presence of the SME
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instructions and registers, and the Linux-specific system interfaces
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described in this document. SME is reported in /proc/cpuinfo as "sme".
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* The presence of SME2 is reported to userspace via HWCAP2_SME2 in the
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aux vector AT_HWCAP2 entry. Presence of this flag implies the presence of
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the SME2 instructions and ZT0, and the Linux-specific system interfaces
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described in this document. SME2 is reported in /proc/cpuinfo as "sme2".
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* Support for the execution of SME instructions in userspace can also be
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detected by reading the CPU ID register ID_AA64PFR1_EL1 using an MRS
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instruction, and checking that the value of the SME field is nonzero. [3]
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@ -44,6 +49,7 @@ model features for SME is included in Appendix A.
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HWCAP2_SME_B16F32
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HWCAP2_SME_F32F32
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HWCAP2_SME_FA64
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HWCAP2_SME2
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This list may be extended over time as the SME architecture evolves.
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@ -52,8 +58,8 @@ model features for SME is included in Appendix A.
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cpu-feature-registers.txt for details.
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* Debuggers should restrict themselves to interacting with the target via the
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NT_ARM_SVE, NT_ARM_SSVE and NT_ARM_ZA regsets. The recommended way
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of detecting support for these regsets is to connect to a target process
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NT_ARM_SVE, NT_ARM_SSVE, NT_ARM_ZA and NT_ARM_ZT regsets. The recommended
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way of detecting support for these regsets is to connect to a target process
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first and then attempt a
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ptrace(PTRACE_GETREGSET, pid, NT_ARM_<regset>, &iov).
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@ -89,13 +95,13 @@ be zeroed.
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-------------------------
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* On syscall PSTATE.ZA is preserved, if PSTATE.ZA==1 then the contents of the
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ZA matrix are preserved.
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ZA matrix and ZTn (if present) are preserved.
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* On syscall PSTATE.SM will be cleared and the SVE registers will be handled
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as per the standard SVE ABI.
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* Neither the SVE registers nor ZA are used to pass arguments to or receive
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results from any syscall.
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* None of the SVE registers, ZA or ZTn are used to pass arguments to
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or receive results from any syscall.
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* On process creation (eg, clone()) the newly created process will have
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PSTATE.SM cleared.
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@ -134,6 +140,14 @@ be zeroed.
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__reserved[] referencing this space. za_context is then written in the
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extra space. Refer to [1] for further details about this mechanism.
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* If ZTn is supported and PSTATE.ZA==1 then a signal frame record for ZTn will
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be generated.
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* The signal record for ZTn has magic ZT_MAGIC (0x5a544e01) and consists of a
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standard signal frame header followed by a struct zt_context specifying
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the number of ZTn registers supported by the system, then zt_context.nregs
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blocks of 64 bytes of data per register.
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5. Signal return
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-----------------
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@ -151,6 +165,9 @@ When returning from a signal handler:
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the signal frame does not match the current vector length, the signal return
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attempt is treated as illegal, resulting in a forced SIGSEGV.
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* If ZTn is not supported or PSTATE.ZA==0 then it is illegal to have a
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signal frame record for ZTn, resulting in a forced SIGSEGV.
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6. prctl extensions
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--------------------
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@ -214,8 +231,8 @@ prctl(PR_SME_SET_VL, unsigned long arg)
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vector length that will be applied at the next execve() by the calling
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thread.
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* Changing the vector length causes all of ZA, P0..P15, FFR and all bits of
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Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become
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* Changing the vector length causes all of ZA, ZTn, P0..P15, FFR and all
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bits of Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become
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unspecified, including both streaming and non-streaming SVE state.
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Calling PR_SME_SET_VL with vl equal to the thread's current vector
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length, or calling PR_SME_SET_VL with the PR_SVE_SET_VL_ONEXEC flag,
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@ -317,6 +334,15 @@ The regset data starts with struct user_za_header, containing:
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* The effect of writing a partial, incomplete payload is unspecified.
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* A new regset NT_ARM_ZT is defined for access to ZTn state via
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PTRACE_GETREGSET and PTRACE_SETREGSET.
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* The NT_ARM_ZT regset consists of a single 512 bit register.
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* When PSTATE.ZA==0 reads of NT_ARM_ZT will report all bits of ZTn as 0.
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* Writes to NT_ARM_ZT will set PSTATE.ZA to 1.
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8. ELF coredump extensions
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---------------------------
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@ -331,6 +357,11 @@ The regset data starts with struct user_za_header, containing:
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been read if a PTRACE_GETREGSET of NT_ARM_ZA were executed for each thread
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when the coredump was generated.
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* A NT_ARM_ZT note will be added to each coredump for each thread of the
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dumped process. The contents will be equivalent to the data that would have
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been read if a PTRACE_GETREGSET of NT_ARM_ZT were executed for each thread
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when the coredump was generated.
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* The NT_ARM_TLS note will be extended to two registers, the second register
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will contain TPIDR2_EL0 on systems that support SME and will be read as
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zero with writes ignored otherwise.
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@ -406,6 +437,9 @@ In A64 state, SME adds the following:
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For best system performance it is strongly encouraged for software to enable
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ZA only when it is actively being used.
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* A new ZT0 register is introduced when SME2 is present. This is a 512 bit
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register which is accessible when PSTATE.ZA is set, as ZA itself is.
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* Two new 1 bit fields in PSTATE which may be controlled via the SMSTART and
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SMSTOP instructions or by access to the SVCR system register:
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