Texas Instruments K3 SoC family changes for 5.3
- Add support for the new J721e SoC, includes basic peripherals needed for booting up the device - New peripheral support added for AM654x: * TI SCI irqchip * GPIO * MCU SRAM * R5Fs * MSMC RAM * SERDES and PCIe -----BEGIN PGP SIGNATURE----- iQJEBAABCAAuFiEEtQ6szHmfiBT7fujkyvq9MXlQGhEFAl0KJB8QHHQta3Jpc3Rv QHRpLmNvbQAKCRDK+r0xeVAaEQf+D/9DkNeB2x9ktkLEdlmVv3hI3kqVTDvxz/8Q S8tLvhzqUmWcGbuEHteAp8Gsu/Zk9niy6bma1F+9NByewWfZUgwrvQEGp4eRgHbl 2d+M0jwPDXzeHpWXXtThP9mXpWiSns8jIvwUovOe+sSwpCfhYQydqhIipQpMVeya b5qKkLgnokVHG0AtK/U6WVAdv+QqHrFkifSwwRK1B8nuU+guzuBMxwkZlFd83axG Y01EknIlKkDlinjL/Hv5FKxNfNeD9a19r+76KCm8CrVvymkwERxxxLdf149yv3hK 6Nmh75tcZJpVE819SY9CQQW5huwRAfpu6Xg/h9qLleUWVG4WsguPqGP68LOGY8Cu AumZIQENo+5iu13L7V3R8k94JJSVbfQIyyH40LnWk89gohBA65WGGBBsXQ6wIPZ0 1j0AxT069oG12Y1WVoiVSxBK6PnF9NzSvgk/oRLObf7HgOzSh6T3Y43ZmzD3IppA omLDOqkgqh2t79u4atIU7ZWCQcp7hEQynLRy3tdp8+sUJx1aGr8LgEDj8p64Q1/Q d+q19jOenpcMHcwSY27r1uO1ddKDxzhGhV+px/3Wdt2OyR33BTvkP67CmeoO2TpZ 8fHXxEq+nroq2u4ciC3sbAAhYdvg1IQKkbmRFtYohbN1ezrGMwc+sGEJrkTrIBBa urtRfY2Hwg== =r10Q -----END PGP SIGNATURE----- Merge tag 'ti-k3-soc-for-v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into arm/dt Texas Instruments K3 SoC family changes for 5.3 - Add support for the new J721e SoC, includes basic peripherals needed for booting up the device - New peripheral support added for AM654x: * TI SCI irqchip * GPIO * MCU SRAM * R5Fs * MSMC RAM * SERDES and PCIe * tag 'ti-k3-soc-for-v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux: (26 commits) arm64: dts: ti: k3-j721e: Add the MCU SRAM node arm64: dts: ti: k3-j721e: Add interrupt controllers in wakeup domain arm64: dts: ti: k3-j721e: Add interrupt controllers in main domain arm64: dts: ti: k3-j721e-main: Add Main NavSS Interrupt controller node arm64: defconfig: Enable TI's J721E SoC platform arm64: dts: ti: Add support for J721E Common Processor Board soc: ti: Add Support for J721E SoC config option arm64: dts: ti: Add Support for J721E SoC dt-bindings: serial: 8250_omap: Add compatible for J721E UART controller dt-bindings: arm: ti: Add bindings for J721E SoC arm64: dts: ti: am654-base-board: Disable SERDES and PCIe arm64: dts: k3-am6: Add PCIe Endpoint DT node arm64: dts: k3-am6: Add PCIe Root Complex DT node arm64: dts: k3-am6: Add SERDES DT node arm64: dts: k3-am6: Add mux-controller DT node required for muxing SERDES arm64: dts: k3-am6: Add "socionext,synquacer-pre-its" property to gic_its arm64: dts: ti: k3-am65: Add MSMC RAM ranges in interconnect node arm64: dts: ti: k3-am65: Add R5F ranges in interconnect nodes arm64: dts: ti: k3-am65-mcu: Add the MCU RAM node arm64: dts: ti: k3-am65: Add MCU SRAM ranges in interconnect nodes ... Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
4ed7e4e578
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@ -13,6 +13,9 @@ architecture it uses, using one of the following compatible values:
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- AM654
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compatible = "ti,am654";
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- J721E
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compatible = "ti,j721e";
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Boards
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------
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@ -1,6 +1,7 @@
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OMAP UART controller
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Required properties:
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- compatible : should be "ti,j721e-uart", "ti,am654-uart" for J721E controllers
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- compatible : should be "ti,am654-uart" for AM654 controllers
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- compatible : should be "ti,omap2-uart" for OMAP2 controllers
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- compatible : should be "ti,omap3-uart" for OMAP3 controllers
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@ -7,3 +7,5 @@
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#
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dtb-$(CONFIG_ARCH_K3_AM6_SOC) += k3-am654-base-board.dtb
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dtb-$(CONFIG_ARCH_K3_J721E_SOC) += k3-j721e-common-proc-board.dtb
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@ -4,6 +4,7 @@
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*
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#include <dt-bindings/phy/phy-am654-serdes.h>
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&cbass_main {
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msmc_ram: sram@70000000 {
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@ -44,6 +45,7 @@
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gic_its: gic-its@18200000 {
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compatible = "arm,gic-v3-its";
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reg = <0x00 0x01820000 0x00 0x10000>;
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socionext,synquacer-pre-its = <0x1000000 0x400000>;
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msi-controller;
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#msi-cells = <1>;
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};
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@ -60,6 +62,36 @@
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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};
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serdes0: serdes@900000 {
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compatible = "ti,phy-am654-serdes";
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reg = <0x0 0x900000 0x0 0x2000>;
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reg-names = "serdes";
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#phy-cells = <2>;
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power-domains = <&k3_pds 153>;
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clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
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clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
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assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
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assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
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ti,serdes-clk = <&serdes0_clk>;
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#clock-cells = <1>;
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mux-controls = <&serdes_mux 0>;
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};
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serdes1: serdes@910000 {
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compatible = "ti,phy-am654-serdes";
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reg = <0x0 0x910000 0x0 0x2000>;
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reg-names = "serdes";
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#phy-cells = <2>;
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power-domains = <&k3_pds 154>;
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clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
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clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
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assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
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assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
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ti,serdes-clk = <&serdes1_clk>;
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#clock-cells = <1>;
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mux-controls = <&serdes_mux 1>;
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};
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main_uart0: serial@2800000 {
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compatible = "ti,am654-uart";
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reg = <0x00 0x02800000 0x00 0x100>;
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@ -232,6 +264,38 @@
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x00100000 0x1c000>;
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pcie0_mode: pcie-mode@4060 {
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compatible = "syscon";
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reg = <0x00004060 0x4>;
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};
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pcie1_mode: pcie-mode@4070 {
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compatible = "syscon";
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reg = <0x00004070 0x4>;
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};
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pcie_devid: pcie-devid@210 {
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compatible = "syscon";
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reg = <0x00000210 0x4>;
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};
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serdes0_clk: serdes_clk@4080 {
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compatible = "syscon";
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reg = <0x00004080 0x4>;
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};
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serdes1_clk: serdes_clk@4090 {
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compatible = "syscon";
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reg = <0x00004090 0x4>;
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};
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serdes_mux: mux-controller {
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compatible = "mmio-mux";
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#mux-control-cells = <1>;
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mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
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<0x4090 0x3>; /* SERDES1 lane select */
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};
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};
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dwc3_0: dwc3@4000000 {
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@ -309,4 +373,141 @@
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clock-names = "wkupclk", "refclk";
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#phy-cells = <0>;
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};
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intr_main_gpio: interrupt-controller0 {
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compatible = "ti,sci-intr";
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ti,intr-trigger-type = <1>;
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interrupt-controller;
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interrupt-parent = <&gic500>;
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#interrupt-cells = <2>;
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ti,sci = <&dmsc>;
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ti,sci-dst-id = <56>;
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ti,sci-rm-range-girq = <0x1>;
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};
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cbass_main_navss: interconnect0 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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intr_main_navss: interrupt-controller1 {
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compatible = "ti,sci-intr";
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ti,intr-trigger-type = <4>;
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interrupt-controller;
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interrupt-parent = <&gic500>;
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#interrupt-cells = <2>;
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ti,sci = <&dmsc>;
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ti,sci-dst-id = <56>;
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ti,sci-rm-range-girq = <0x0>, <0x2>;
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};
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inta_main_udmass: interrupt-controller@33d00000 {
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compatible = "ti,sci-inta";
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reg = <0x0 0x33d00000 0x0 0x100000>;
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interrupt-controller;
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interrupt-parent = <&intr_main_navss>;
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msi-controller;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <179>;
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ti,sci-rm-range-vint = <0x0>;
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ti,sci-rm-range-global-event = <0x1>;
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};
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};
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main_gpio0: main_gpio0@600000 {
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compatible = "ti,am654-gpio", "ti,keystone-gpio";
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reg = <0x0 0x600000 0x0 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&intr_main_gpio>;
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interrupts = <57 256>, <57 257>, <57 258>, <57 259>, <57 260>,
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<57 261>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <96>;
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ti,davinci-gpio-unbanked = <0>;
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clocks = <&k3_clks 57 0>;
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clock-names = "gpio";
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};
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main_gpio1: main_gpio1@601000 {
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compatible = "ti,am654-gpio", "ti,keystone-gpio";
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reg = <0x0 0x601000 0x0 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&intr_main_gpio>;
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interrupts = <58 256>, <58 257>, <58 258>, <58 259>, <58 260>,
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<58 261>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <90>;
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ti,davinci-gpio-unbanked = <0>;
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clocks = <&k3_clks 58 0>;
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clock-names = "gpio";
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};
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pcie0_rc: pcie@5500000 {
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compatible = "ti,am654-pcie-rc";
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reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
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reg-names = "app", "dbics", "config", "atu";
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power-domains = <&k3_pds 120>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000
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0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
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ti,syscon-pcie-id = <&pcie_devid>;
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ti,syscon-pcie-mode = <&pcie0_mode>;
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bus-range = <0x0 0xff>;
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num-viewport = <16>;
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max-link-speed = <3>;
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dma-coherent;
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interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
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msi-map = <0x0 &gic_its 0x0 0x10000>;
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};
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pcie0_ep: pcie-ep@5500000 {
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compatible = "ti,am654-pcie-ep";
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reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
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reg-names = "app", "dbics", "addr_space", "atu";
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power-domains = <&k3_pds 120>;
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ti,syscon-pcie-mode = <&pcie0_mode>;
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num-ib-windows = <16>;
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num-ob-windows = <16>;
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max-link-speed = <3>;
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dma-coherent;
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interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
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};
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pcie1_rc: pcie@5600000 {
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compatible = "ti,am654-pcie-rc";
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reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
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reg-names = "app", "dbics", "config", "atu";
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power-domains = <&k3_pds 121>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000
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0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
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ti,syscon-pcie-id = <&pcie_devid>;
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ti,syscon-pcie-mode = <&pcie1_mode>;
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bus-range = <0x0 0xff>;
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num-viewport = <16>;
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max-link-speed = <3>;
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dma-coherent;
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interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
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msi-map = <0x0 &gic_its 0x10000 0x10000>;
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};
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pcie1_ep: pcie-ep@5600000 {
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compatible = "ti,am654-pcie-ep";
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reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
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reg-names = "app", "dbics", "addr_space", "atu";
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power-domains = <&k3_pds 121>;
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ti,syscon-pcie-mode = <&pcie1_mode>;
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num-ib-windows = <16>;
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num-ob-windows = <16>;
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max-link-speed = <3>;
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dma-coherent;
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interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
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};
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};
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@ -17,6 +17,14 @@
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power-domains = <&k3_pds 149>;
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};
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mcu_ram: sram@41c00000 {
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compatible = "mmio-sram";
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reg = <0x00 0x41c00000 0x00 0x80000>;
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ranges = <0x0 0x00 0x41c00000 0x80000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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mcu_i2c0: i2c@40b00000 {
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compatible = "ti,am654-i2c", "ti,omap4-i2c";
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reg = <0x0 0x40b00000 0x0 0x100>;
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@ -7,7 +7,7 @@
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&cbass_wakeup {
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dmsc: dmsc {
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compatible = "ti,k2g-sci";
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compatible = "ti,am654-sci";
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ti,host-id = <12>;
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#address-cells = <1>;
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#size-cells = <1>;
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@ -63,4 +63,30 @@
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clocks = <&k3_clks 115 1>;
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power-domains = <&k3_pds 115>;
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};
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intr_wkup_gpio: interrupt-controller2 {
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compatible = "ti,sci-intr";
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ti,intr-trigger-type = <1>;
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interrupt-controller;
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interrupt-parent = <&gic500>;
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#interrupt-cells = <2>;
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ti,sci = <&dmsc>;
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ti,sci-dst-id = <56>;
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ti,sci-rm-range-girq = <0x4>;
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};
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wkup_gpio0: wkup_gpio0@42110000 {
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compatible = "ti,am654-gpio", "ti,keystone-gpio";
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reg = <0x42110000 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&intr_wkup_gpio>;
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interrupts = <59 128>, <59 129>, <59 130>, <59 131>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <56>;
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ti,davinci-gpio-unbanked = <0>;
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clocks = <&k3_clks 59 0>;
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clock-names = "gpio";
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};
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};
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@ -68,9 +68,14 @@
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<0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
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<0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
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<0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
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<0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
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<0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
|
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/* MCUSS Range */
|
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<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
|
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<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
|
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<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
|
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<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
|
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<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>,
|
||||
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
|
||||
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
|
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<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
|
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@ -82,6 +87,9 @@
|
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#size-cells = <2>;
|
||||
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
|
||||
<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
|
||||
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
|
||||
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
|
||||
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */
|
||||
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
|
||||
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
|
||||
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "k3-am654.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
compatible = "ti,am654-evm", "ti,am654";
|
||||
|
|
@ -33,6 +34,25 @@
|
|||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
autorepeat;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&push_button_pins_default>;
|
||||
|
||||
sw5 {
|
||||
label = "GPIO Key USER1";
|
||||
linux,code = <BTN_0>;
|
||||
gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
sw6 {
|
||||
label = "GPIO Key USER2";
|
||||
linux,code = <BTN_1>;
|
||||
gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_pmx0 {
|
||||
|
|
@ -42,6 +62,13 @@
|
|||
AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
push_button_pins_default: push_button__pins_default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */
|
||||
AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
|
|
@ -228,3 +255,27 @@
|
|||
ti,adc-channels = <0 1 2 3 4 5 6 7>;
|
||||
};
|
||||
};
|
||||
|
||||
&serdes0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&serdes1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie0_rc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie0_ep {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie1_rc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie1_ep {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,50 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-j721e-som-p0.dtsi"
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_uart0 {
|
||||
/* Wakeup UART is used by System firmware */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart3 {
|
||||
/* UART not brought out */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart5 {
|
||||
/* UART not brought out */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart6 {
|
||||
/* UART not brought out */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart7 {
|
||||
/* UART not brought out */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart8 {
|
||||
/* UART not brought out */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart9 {
|
||||
/* UART not brought out */
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -0,0 +1,243 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for J721E SoC Family Main Domain peripherals
|
||||
*
|
||||
* Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*/
|
||||
|
||||
&cbass_main {
|
||||
msmc_ram: sram@70000000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x0 0x70000000 0x0 0x800000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x70000000 0x800000>;
|
||||
|
||||
atf-sram@0 {
|
||||
reg = <0x0 0x20000>;
|
||||
};
|
||||
};
|
||||
|
||||
gic500: interrupt-controller@1800000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
|
||||
<0x00 0x01900000 0x00 0x100000>; /* GICR */
|
||||
|
||||
/* vcpumntirq: virtual CPU interface maintenance interrupt */
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
gic_its: gic-its@18200000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
reg = <0x00 0x01820000 0x00 0x10000>;
|
||||
socionext,synquacer-pre-its = <0x1000000 0x400000>;
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
smmu0: smmu@36600000 {
|
||||
compatible = "arm,smmu-v3";
|
||||
reg = <0x0 0x36600000 0x0 0x100000>;
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "eventq", "gerror";
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
main_gpio_intr: interrupt-controller0 {
|
||||
compatible = "ti,sci-intr";
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <2>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dst-id = <14>;
|
||||
ti,sci-rm-range-girq = <0x1>;
|
||||
};
|
||||
|
||||
cbass_main_navss: interconnect0 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
main_navss_intr: interrupt-controller1 {
|
||||
compatible = "ti,sci-intr";
|
||||
ti,intr-trigger-type = <4>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <2>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dst-id = <14>;
|
||||
ti,sci-rm-range-girq = <0>, <2>;
|
||||
};
|
||||
|
||||
main_udmass_inta: interrupt-controller@33d00000 {
|
||||
compatible = "ti,sci-inta";
|
||||
reg = <0x0 0x33d00000 0x0 0x100000>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
msi-controller;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <209>;
|
||||
ti,sci-rm-range-vint = <0xa>;
|
||||
ti,sci-rm-range-global-event = <0xd>;
|
||||
};
|
||||
};
|
||||
|
||||
secure_proxy_main: mailbox@32c00000 {
|
||||
compatible = "ti,am654-secure-proxy";
|
||||
#mbox-cells = <1>;
|
||||
reg-names = "target_data", "rt", "scfg";
|
||||
reg = <0x00 0x32c00000 0x00 0x100000>,
|
||||
<0x00 0x32400000 0x00 0x100000>,
|
||||
<0x00 0x32800000 0x00 0x100000>;
|
||||
interrupt-names = "rx_011";
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
main_pmx0: pinmux@11c000 {
|
||||
compatible = "pinctrl-single";
|
||||
/* Proxy 0 addressing */
|
||||
reg = <0x0 0x11c000 0x0 0x2b4>;
|
||||
#pinctrl-cells = <1>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
main_uart0: serial@2800000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02800000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 146>;
|
||||
clocks = <&k3_clks 146 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
main_uart1: serial@2810000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02810000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 278>;
|
||||
clocks = <&k3_clks 278 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
main_uart2: serial@2820000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02820000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 279>;
|
||||
clocks = <&k3_clks 279 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
main_uart3: serial@2830000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02830000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 280>;
|
||||
clocks = <&k3_clks 280 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
main_uart4: serial@2840000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02840000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 281>;
|
||||
clocks = <&k3_clks 281 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
main_uart5: serial@2850000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02850000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 282>;
|
||||
clocks = <&k3_clks 282 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
main_uart6: serial@2860000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02860000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 283>;
|
||||
clocks = <&k3_clks 283 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
main_uart7: serial@2870000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02870000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 284>;
|
||||
clocks = <&k3_clks 284 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
main_uart8: serial@2880000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02880000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 285>;
|
||||
clocks = <&k3_clks 285 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
main_uart9: serial@2890000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02890000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 286>;
|
||||
clocks = <&k3_clks 286 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,90 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
|
||||
*
|
||||
* Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*/
|
||||
|
||||
&cbass_mcu_wakeup {
|
||||
dmsc: dmsc@44083000 {
|
||||
compatible = "ti,k2g-sci";
|
||||
ti,host-id = <12>;
|
||||
|
||||
mbox-names = "rx", "tx";
|
||||
|
||||
mboxes= <&secure_proxy_main 11>,
|
||||
<&secure_proxy_main 13>;
|
||||
|
||||
reg-names = "debug_messages";
|
||||
reg = <0x00 0x44083000 0x0 0x1000>;
|
||||
|
||||
k3_pds: power-controller {
|
||||
compatible = "ti,sci-pm-domain";
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
k3_clks: clocks {
|
||||
compatible = "ti,k2g-sci-clk";
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
||||
k3_reset: reset-controller {
|
||||
compatible = "ti,sci-reset";
|
||||
#reset-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
wkup_pmx0: pinmux@4301c000 {
|
||||
compatible = "pinctrl-single";
|
||||
/* Proxy 0 addressing */
|
||||
reg = <0x00 0x4301c000 0x00 0x178>;
|
||||
#pinctrl-cells = <1>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
mcu_ram: sram@41c00000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00 0x41c00000 0x00 0x100000>;
|
||||
ranges = <0x0 0x00 0x41c00000 0x100000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
wkup_uart0: serial@42300000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x42300000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 287>;
|
||||
clocks = <&k3_clks 287 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
mcu_uart0: serial@40a00000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x40a00000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <96000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 149>;
|
||||
clocks = <&k3_clks 149 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
wkup_gpio_intr: interrupt-controller2 {
|
||||
compatible = "ti,sci-intr";
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <2>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dst-id = <14>;
|
||||
ti,sci-rm-range-girq = <0x5>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-j721e.dtsi"
|
||||
|
||||
/ {
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 4G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
|
||||
<0x00000008 0x80000000 0x00000000 0x80000000>;
|
||||
};
|
||||
|
||||
reserved_memory: reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
secure_ddr: optee@9e800000 {
|
||||
reg = <0x00 0x9e800000 0x00 0x01800000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,177 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for J721E SoC Family
|
||||
*
|
||||
* Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/k3.h>
|
||||
|
||||
/ {
|
||||
model = "Texas Instruments K3 J721E SoC";
|
||||
compatible = "ti,j721e";
|
||||
interrupt-parent = <&gic500>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
serial0 = &wkup_uart0;
|
||||
serial1 = &mcu_uart0;
|
||||
serial2 = &main_uart0;
|
||||
serial3 = &main_uart1;
|
||||
serial4 = &main_uart2;
|
||||
serial5 = &main_uart3;
|
||||
serial6 = &main_uart4;
|
||||
serial7 = &main_uart5;
|
||||
serial8 = &main_uart6;
|
||||
serial9 = &main_uart7;
|
||||
serial10 = &main_uart8;
|
||||
serial11 = &main_uart9;
|
||||
};
|
||||
|
||||
chosen { };
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu-map {
|
||||
cluster0: cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x000>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x001>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-size = <0x100000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <2048>;
|
||||
next-level-cache = <&msmc_l3>;
|
||||
};
|
||||
|
||||
msmc_l3: l3-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <3>;
|
||||
};
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
psci: psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
||||
a72_timer0: timer-cl0-cpu0 {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
|
||||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
/* Recommendation from GIC500 TRM Table A.3 */
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
cbass_main: interconnect@100000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
|
||||
<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
|
||||
<0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
|
||||
<0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */
|
||||
<0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
|
||||
<0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
|
||||
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/
|
||||
<0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
|
||||
<0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
|
||||
<0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
|
||||
<0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */
|
||||
<0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
|
||||
<0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
|
||||
|
||||
/* MCUSS_WKUP Range */
|
||||
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
|
||||
<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
|
||||
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
|
||||
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
|
||||
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
|
||||
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
|
||||
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
|
||||
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
|
||||
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
|
||||
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
|
||||
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
|
||||
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
|
||||
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
|
||||
|
||||
cbass_mcu_wakeup: interconnect@28380000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
|
||||
<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
|
||||
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
|
||||
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
|
||||
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
|
||||
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
|
||||
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
|
||||
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
|
||||
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
|
||||
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
|
||||
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
|
||||
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
|
||||
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Now include the peripherals for each bus segments */
|
||||
#include "k3-j721e-main.dtsi"
|
||||
#include "k3-j721e-mcu-wakeup.dtsi"
|
||||
|
|
@ -696,6 +696,7 @@ CONFIG_ARCH_TEGRA_210_SOC=y
|
|||
CONFIG_ARCH_TEGRA_186_SOC=y
|
||||
CONFIG_ARCH_TEGRA_194_SOC=y
|
||||
CONFIG_ARCH_K3_AM6_SOC=y
|
||||
CONFIG_ARCH_K3_J721E_SOC=y
|
||||
CONFIG_SOC_TI=y
|
||||
CONFIG_TI_SCI_PM_DOMAINS=y
|
||||
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
|
||||
|
|
|
|||
|
|
@ -9,6 +9,11 @@ config ARCH_K3_AM6_SOC
|
|||
help
|
||||
Enable support for TI's AM6 SoC Family support
|
||||
|
||||
config ARCH_K3_J721E_SOC
|
||||
bool "K3 J721E SoC"
|
||||
help
|
||||
Enable support for TI's J721E SoC Family support
|
||||
|
||||
endif
|
||||
|
||||
endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue