ath9k: INI update for AR9285 and periodic PA offset caliberation
This patch updates the initvalues for AR9285 chipset and also adds periodic PA offset caliberation. Signed-off-by: Senthil Balasubramanian <senthilkumar@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Senthil Balasubramanian
John W. Linville
parent
b03a9db95a
commit
4e84516838
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@ -745,43 +745,6 @@ static void ath9k_olc_temp_compensation(struct ath_hw *ah)
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}
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}
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bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
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u8 rxchainmask, bool longcal,
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bool *isCalDone)
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{
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struct hal_cal_list *currCal = ah->cal_list_curr;
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*isCalDone = true;
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if (currCal &&
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(currCal->calState == CAL_RUNNING ||
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currCal->calState == CAL_WAITING)) {
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ath9k_hw_per_calibration(ah, chan, rxchainmask, currCal,
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isCalDone);
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if (*isCalDone) {
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ah->cal_list_curr = currCal = currCal->calNext;
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if (currCal->calState == CAL_WAITING) {
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*isCalDone = false;
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ath9k_hw_reset_calibration(ah, currCal);
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}
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}
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}
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if (longcal) {
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if (OLC_FOR_AR9280_20_LATER)
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ath9k_olc_temp_compensation(ah);
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ath9k_hw_getnf(ah, chan);
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ath9k_hw_loadnf(ah, ah->curchan);
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ath9k_hw_start_nfcal(ah);
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if (chan->channelFlags & CHANNEL_CW_INT)
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chan->channelFlags &= ~CHANNEL_CW_INT;
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}
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return true;
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}
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static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah)
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{
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@ -877,22 +840,104 @@ static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah)
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}
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bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
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u8 rxchainmask, bool longcal,
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bool *isCalDone)
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{
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struct hal_cal_list *currCal = ah->cal_list_curr;
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*isCalDone = true;
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if (currCal &&
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(currCal->calState == CAL_RUNNING ||
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currCal->calState == CAL_WAITING)) {
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ath9k_hw_per_calibration(ah, chan, rxchainmask, currCal,
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isCalDone);
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if (*isCalDone) {
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ah->cal_list_curr = currCal = currCal->calNext;
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if (currCal->calState == CAL_WAITING) {
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*isCalDone = false;
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ath9k_hw_reset_calibration(ah, currCal);
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}
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}
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}
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if (longcal) {
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if (AR_SREV_9285(ah) && AR_SREV_9285_11_OR_LATER(ah))
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ath9k_hw_9285_pa_cal(ah);
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if (OLC_FOR_AR9280_20_LATER)
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ath9k_olc_temp_compensation(ah);
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ath9k_hw_getnf(ah, chan);
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ath9k_hw_loadnf(ah, ah->curchan);
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ath9k_hw_start_nfcal(ah);
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if (chan->channelFlags & CHANNEL_CW_INT)
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chan->channelFlags &= ~CHANNEL_CW_INT;
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}
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return true;
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}
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bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
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{
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REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
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if (chan->channelFlags & CHANNEL_HT20) {
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REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
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REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
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REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
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AR_PHY_AGC_CONTROL_FLTR_CAL);
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REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
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REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
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if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
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AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
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DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "offset "
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"calibration failed to complete in "
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"1ms; noisy ??\n");
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return false;
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}
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REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
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REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
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REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
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}
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REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
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REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
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REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
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REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
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if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
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0, AH_WAIT_TIMEOUT)) {
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DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "offset calibration "
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"failed to complete in 1ms; noisy ??\n");
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return false;
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}
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REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
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REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
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REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
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return true;
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}
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bool ath9k_hw_init_cal(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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if (AR_SREV_9280_10_OR_LATER(ah)) {
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if (AR_SREV_9285(ah) && AR_SREV_9285_12_OR_LATER(ah)) {
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if (!ar9285_clc(ah, chan))
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return false;
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} else if (AR_SREV_9280_10_OR_LATER(ah)) {
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REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
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REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
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REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
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/* Kick off the cal */
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REG_WRITE(ah, AR_PHY_AGC_CONTROL,
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REG_READ(ah, AR_PHY_AGC_CONTROL) |
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AR_PHY_AGC_CONTROL_CAL);
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REG_READ(ah, AR_PHY_AGC_CONTROL) |
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AR_PHY_AGC_CONTROL_CAL);
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if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
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AR_PHY_AGC_CONTROL_CAL, 0,
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AH_WAIT_TIMEOUT)) {
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AR_PHY_AGC_CONTROL_CAL, 0,
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AH_WAIT_TIMEOUT)) {
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DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
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"offset calibration failed to complete in 1ms; "
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"noisy environment?\n");
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@ -906,11 +951,11 @@ bool ath9k_hw_init_cal(struct ath_hw *ah,
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/* Calibrate the AGC */
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REG_WRITE(ah, AR_PHY_AGC_CONTROL,
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REG_READ(ah, AR_PHY_AGC_CONTROL) |
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AR_PHY_AGC_CONTROL_CAL);
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REG_READ(ah, AR_PHY_AGC_CONTROL) |
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AR_PHY_AGC_CONTROL_CAL);
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if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
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0, AH_WAIT_TIMEOUT)) {
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0, AH_WAIT_TIMEOUT)) {
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DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
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"offset calibration failed to complete in 1ms; "
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"noisy environment?\n");
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@ -928,8 +973,8 @@ bool ath9k_hw_init_cal(struct ath_hw *ah,
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/* Do NF Calibration */
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REG_WRITE(ah, AR_PHY_AGC_CONTROL,
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REG_READ(ah, AR_PHY_AGC_CONTROL) |
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AR_PHY_AGC_CONTROL_NF);
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REG_READ(ah, AR_PHY_AGC_CONTROL) |
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AR_PHY_AGC_CONTROL_NF);
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ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
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@ -938,19 +983,19 @@ bool ath9k_hw_init_cal(struct ath_hw *ah,
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INIT_CAL(&ah->adcgain_caldata);
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INSERT_CAL(ah, &ah->adcgain_caldata);
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DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
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"enabling ADC Gain Calibration.\n");
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"enabling ADC Gain Calibration.\n");
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}
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if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {
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INIT_CAL(&ah->adcdc_caldata);
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INSERT_CAL(ah, &ah->adcdc_caldata);
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DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
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"enabling ADC DC Calibration.\n");
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"enabling ADC DC Calibration.\n");
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}
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if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
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INIT_CAL(&ah->iq_caldata);
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INSERT_CAL(ah, &ah->iq_caldata);
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DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
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"enabling IQ Calibration.\n");
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"enabling IQ Calibration.\n");
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}
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ah->cal_list_curr = ah->cal_list;
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@ -261,7 +261,7 @@ struct base_eep_header_4k {
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u16 deviceCap;
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u32 binBuildNumber;
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u8 deviceType;
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u8 futureBase[1];
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u8 txGainType;
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} __packed;
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@ -678,6 +678,7 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
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ah->hw_version.macVersion, ah->hw_version.macRev);
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if (AR_SREV_9285_12_OR_LATER(ah)) {
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INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
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ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
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INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
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@ -817,6 +818,22 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
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if (ecode != 0)
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goto bad;
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if (AR_SREV_9285_12_OR_LATER(ah)) {
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u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
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/* txgain table */
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if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9285Modes_high_power_tx_gain_9285_1_2,
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ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
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} else {
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9285Modes_original_tx_gain_9285_1_2,
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ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
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}
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}
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/* rxgain table */
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if (AR_SREV_9280_20(ah))
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ath9k_hw_init_rxgain_ini(ah);
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@ -1293,7 +1310,8 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
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if (AR_SREV_9280(ah))
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REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
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if (AR_SREV_9280(ah))
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if (AR_SREV_9280(ah) || (AR_SREV_9285(ah) &&
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AR_SREV_9285_12_OR_LATER(ah)))
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REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
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for (i = 0; i < ah->iniCommon.ia_rows; i++) {
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@ -4121,6 +4121,7 @@ static const u_int32_t ar9285PciePhy_clkreq_off_L1_9285[][2] = {
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{0x00004044, 0x00000000 },
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};
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/* AR9285 v1_2 PCI Register Writes. Created: 03/04/09 */
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static const u_int32_t ar9285Modes_9285_1_2[][6] = {
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{ 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
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{ 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
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@ -4155,7 +4156,7 @@ static const u_int32_t ar9285Modes_9285_1_2[][6] = {
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{ 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
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{ 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
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{ 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
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{ 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
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{ 0x000099c8, 0x6af65329, 0x6af65329, 0x6af65329, 0x6af65329, 0x6af65329 },
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{ 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
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{ 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
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{ 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
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@ -4421,25 +4422,6 @@ static const u_int32_t ar9285Modes_9285_1_2[][6] = {
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{ 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
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{ 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
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{ 0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000, 0x0004a000 },
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{ 0x0000a274, 0x0a81c652, 0x0a81c652, 0x0a820652, 0x0a820652, 0x0a82a652 },
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{ 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
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{ 0x0000a304, 0x00000000, 0x00000000, 0x00007201, 0x00007201, 0x00000000 },
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{ 0x0000a308, 0x00000000, 0x00000000, 0x00010408, 0x00010408, 0x00000000 },
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{ 0x0000a30c, 0x00000000, 0x00000000, 0x0001860a, 0x0001860a, 0x00000000 },
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{ 0x0000a310, 0x00000000, 0x00000000, 0x00020818, 0x00020818, 0x00000000 },
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{ 0x0000a314, 0x00000000, 0x00000000, 0x00024858, 0x00024858, 0x00000000 },
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{ 0x0000a318, 0x00000000, 0x00000000, 0x00026859, 0x00026859, 0x00000000 },
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{ 0x0000a31c, 0x00000000, 0x00000000, 0x0002985b, 0x0002985b, 0x00000000 },
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{ 0x0000a320, 0x00000000, 0x00000000, 0x0002b89a, 0x0002b89a, 0x00000000 },
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{ 0x0000a324, 0x00000000, 0x00000000, 0x0002d89b, 0x0002d89b, 0x00000000 },
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{ 0x0000a328, 0x00000000, 0x00000000, 0x0002f89c, 0x0002f89c, 0x00000000 },
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{ 0x0000a32c, 0x00000000, 0x00000000, 0x0003189d, 0x0003189d, 0x00000000 },
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{ 0x0000a330, 0x00000000, 0x00000000, 0x0003389e, 0x0003389e, 0x00000000 },
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{ 0x0000a334, 0x00000000, 0x00000000, 0x000368de, 0x000368de, 0x00000000 },
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{ 0x0000a338, 0x00000000, 0x00000000, 0x0003891e, 0x0003891e, 0x00000000 },
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{ 0x0000a33c, 0x00000000, 0x00000000, 0x0003a95e, 0x0003a95e, 0x00000000 },
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{ 0x0000a340, 0x00000000, 0x00000000, 0x0003e9df, 0x0003e9df, 0x00000000 },
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{ 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
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{ 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
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};
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@ -4569,7 +4551,7 @@ static const u_int32_t ar9285Common_9285_1_2[][2] = {
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{ 0x00008110, 0x00000168 },
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{ 0x00008118, 0x000100aa },
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{ 0x0000811c, 0x00003210 },
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{ 0x00008120, 0x08f04800 },
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{ 0x00008120, 0x08f04810 },
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{ 0x00008124, 0x00000000 },
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{ 0x00008128, 0x00000000 },
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{ 0x0000812c, 0x00000000 },
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@ -4585,7 +4567,7 @@ static const u_int32_t ar9285Common_9285_1_2[][2] = {
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{ 0x00008178, 0x00000100 },
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{ 0x0000817c, 0x00000000 },
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{ 0x000081c0, 0x00000000 },
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{ 0x000081d0, 0x00003210 },
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{ 0x000081d0, 0x0000320a },
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{ 0x000081ec, 0x00000000 },
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{ 0x000081f0, 0x00000000 },
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{ 0x000081f4, 0x00000000 },
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@ -4709,8 +4691,6 @@ static const u_int32_t ar9285Common_9285_1_2[][2] = {
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{ 0x0000a268, 0x00000000 },
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{ 0x0000a26c, 0x0ebae9e6 },
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{ 0x0000d270, 0x0d820820 },
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{ 0x0000a278, 0x318c6318 },
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{ 0x0000a27c, 0x050c0318 },
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{ 0x0000d35c, 0x07ffffef },
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{ 0x0000d360, 0x0fffffe7 },
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{ 0x0000d364, 0x17ffffe5 },
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@ -4725,8 +4705,6 @@ static const u_int32_t ar9285Common_9285_1_2[][2] = {
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{ 0x0000a388, 0x0c000000 },
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{ 0x0000a38c, 0x20202020 },
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{ 0x0000a390, 0x20202020 },
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{ 0x0000a394, 0x318c6318 },
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{ 0x0000a398, 0x00000318 },
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{ 0x0000a39c, 0x00000001 },
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{ 0x0000a3a0, 0x00000000 },
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{ 0x0000a3a4, 0x00000000 },
|
||||
|
|
@ -4741,8 +4719,6 @@ static const u_int32_t ar9285Common_9285_1_2[][2] = {
|
|||
{ 0x0000a3cc, 0x20202020 },
|
||||
{ 0x0000a3d0, 0x20202020 },
|
||||
{ 0x0000a3d4, 0x20202020 },
|
||||
{ 0x0000a3dc, 0x318c6318 },
|
||||
{ 0x0000a3e0, 0x00000318 },
|
||||
{ 0x0000a3e4, 0x00000000 },
|
||||
{ 0x0000a3e8, 0x18c43433 },
|
||||
{ 0x0000a3ec, 0x00f70081 },
|
||||
|
|
@ -4753,13 +4729,11 @@ static const u_int32_t ar9285Common_9285_1_2[][2] = {
|
|||
{ 0x00007810, 0x71c0d388 },
|
||||
{ 0x00007814, 0x924934a8 },
|
||||
{ 0x0000781c, 0x00000000 },
|
||||
{ 0x00007820, 0x00000c04 },
|
||||
{ 0x00007824, 0x00d86fff },
|
||||
{ 0x00007828, 0x26d2491b },
|
||||
{ 0x0000782c, 0x6e36d97b },
|
||||
{ 0x00007830, 0xedb6d96e },
|
||||
{ 0x00007834, 0x71400087 },
|
||||
{ 0x00007838, 0xfac68801 },
|
||||
{ 0x0000783c, 0x0001fffe },
|
||||
{ 0x00007840, 0xffeb1a20 },
|
||||
{ 0x00007844, 0x000c0db6 },
|
||||
|
|
@ -4772,10 +4746,81 @@ static const u_int32_t ar9285Common_9285_1_2[][2] = {
|
|||
{ 0x00007860, 0x21084210 },
|
||||
{ 0x00007864, 0xf7d7ffde },
|
||||
{ 0x00007868, 0xc2034080 },
|
||||
{ 0x0000786c, 0x48609eb4 },
|
||||
{ 0x00007870, 0x10142c00 },
|
||||
};
|
||||
|
||||
static const u_int32_t ar9285Modes_high_power_tx_gain_9285_1_2[][6] = {
|
||||
/* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
|
||||
{ 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x0000a304, 0x00000000, 0x00000000, 0x00005200, 0x00005200, 0x00000000 },
|
||||
{ 0x0000a308, 0x00000000, 0x00000000, 0x00007201, 0x00007201, 0x00000000 },
|
||||
{ 0x0000a30c, 0x00000000, 0x00000000, 0x0000b240, 0x0000b240, 0x00000000 },
|
||||
{ 0x0000a310, 0x00000000, 0x00000000, 0x0000d241, 0x0000d241, 0x00000000 },
|
||||
{ 0x0000a314, 0x00000000, 0x00000000, 0x0000f440, 0x0000f440, 0x00000000 },
|
||||
{ 0x0000a318, 0x00000000, 0x00000000, 0x00014640, 0x00014640, 0x00000000 },
|
||||
{ 0x0000a31c, 0x00000000, 0x00000000, 0x00018680, 0x00018680, 0x00000000 },
|
||||
{ 0x0000a320, 0x00000000, 0x00000000, 0x00019841, 0x00019841, 0x00000000 },
|
||||
{ 0x0000a324, 0x00000000, 0x00000000, 0x0001ca40, 0x0001ca40, 0x00000000 },
|
||||
{ 0x0000a328, 0x00000000, 0x00000000, 0x0001fa80, 0x0001fa80, 0x00000000 },
|
||||
{ 0x0000a32c, 0x00000000, 0x00000000, 0x00023ac0, 0x00023ac0, 0x00000000 },
|
||||
{ 0x0000a330, 0x00000000, 0x00000000, 0x0002ab40, 0x0002ab40, 0x00000000 },
|
||||
{ 0x0000a334, 0x00000000, 0x00000000, 0x00033d82, 0x00033d82, 0x00000000 },
|
||||
{ 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
|
||||
{ 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
|
||||
{ 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x00007838, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803 },
|
||||
{ 0x0000786c, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe },
|
||||
{ 0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00 },
|
||||
{ 0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a21a652, 0x0a21a652, 0x0a22a652 },
|
||||
{ 0x0000a278, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce },
|
||||
{ 0x0000a27c, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce },
|
||||
{ 0x0000a394, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce },
|
||||
{ 0x0000a398, 0x000001ce, 0x000001ce, 0x000001ce, 0x000001ce, 0x000001ce },
|
||||
{ 0x0000a3dc, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce },
|
||||
{ 0x0000a3e0, 0x000001ce, 0x000001ce, 0x000001ce, 0x000001ce, 0x000001ce },
|
||||
};
|
||||
|
||||
static const u_int32_t ar9285Modes_original_tx_gain_9285_1_2[][6] = {
|
||||
/* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
|
||||
{ 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 },
|
||||
{ 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 },
|
||||
{ 0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608, 0x00000000 },
|
||||
{ 0x0000a310, 0x00000000, 0x00000000, 0x00022618, 0x00022618, 0x00000000 },
|
||||
{ 0x0000a314, 0x00000000, 0x00000000, 0x0002a6c9, 0x0002a6c9, 0x00000000 },
|
||||
{ 0x0000a318, 0x00000000, 0x00000000, 0x00031710, 0x00031710, 0x00000000 },
|
||||
{ 0x0000a31c, 0x00000000, 0x00000000, 0x00035718, 0x00035718, 0x00000000 },
|
||||
{ 0x0000a320, 0x00000000, 0x00000000, 0x00038758, 0x00038758, 0x00000000 },
|
||||
{ 0x0000a324, 0x00000000, 0x00000000, 0x0003c75a, 0x0003c75a, 0x00000000 },
|
||||
{ 0x0000a328, 0x00000000, 0x00000000, 0x0004075c, 0x0004075c, 0x00000000 },
|
||||
{ 0x0000a32c, 0x00000000, 0x00000000, 0x0004475e, 0x0004475e, 0x00000000 },
|
||||
{ 0x0000a330, 0x00000000, 0x00000000, 0x0004679f, 0x0004679f, 0x00000000 },
|
||||
{ 0x0000a334, 0x00000000, 0x00000000, 0x000487df, 0x000487df, 0x00000000 },
|
||||
{ 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
|
||||
{ 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
|
||||
{ 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x00007838, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801 },
|
||||
{ 0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4 },
|
||||
{ 0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04 },
|
||||
{ 0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a21a652, 0x0a21a652, 0x0a22a652 },
|
||||
{ 0x0000a278, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
|
||||
{ 0x0000a27c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c },
|
||||
{ 0x0000a394, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
|
||||
{ 0x0000a398, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
|
||||
{ 0x0000a3dc, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
|
||||
{ 0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
|
||||
};
|
||||
|
||||
static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_9285_1_2[][2] = {
|
||||
{0x00004040, 0x9248fd00 },
|
||||
{0x00004040, 0x24924924 },
|
||||
|
|
|
|||
|
|
@ -446,6 +446,9 @@ bool ath9k_hw_init_rf(struct ath_hw *ah,
|
|||
#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
|
||||
#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
|
||||
|
||||
#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
|
||||
#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
|
||||
|
||||
#define AR_PHY_TX_PWRCTRL4 0xa264
|
||||
#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001
|
||||
#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0
|
||||
|
|
@ -513,6 +516,7 @@ bool ath9k_hw_init_rf(struct ath_hw *ah,
|
|||
/* Carrier leak calibration control, do it after AGC calibration */
|
||||
#define AR_PHY_CL_CAL_CTL 0xA358
|
||||
#define AR_PHY_CL_CAL_ENABLE 0x00000002
|
||||
#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
|
||||
|
||||
#define AR_PHY_POWER_TX_RATE5 0xA38C
|
||||
#define AR_PHY_POWER_TX_RATE6 0xA390
|
||||
|
|
|
|||
Loading…
Reference in New Issue