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drm/nouveau/gpio: switch to device pri macros 

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2015-08-20 14:54:09 +10:00
parent 2bdb4995fd
commit 4de93a086e
5 changed files with 60 additions and 44 deletions
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22
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c
View File

@ -26,21 +26,23 @@
void void
g94_gpio_intr_stat(struct nvkm_gpio *gpio, u32 *hi, u32 *lo) g94_gpio_intr_stat(struct nvkm_gpio *gpio, u32 *hi, u32 *lo)
{ {
u32 intr0 = nv_rd32(gpio, 0x00e054); struct nvkm_device *device = gpio->subdev.device;
u32 intr1 = nv_rd32(gpio, 0x00e074); u32 intr0 = nvkm_rd32(device, 0x00e054);
u32 stat0 = nv_rd32(gpio, 0x00e050) & intr0; u32 intr1 = nvkm_rd32(device, 0x00e074);
u32 stat1 = nv_rd32(gpio, 0x00e070) & intr1; u32 stat0 = nvkm_rd32(device, 0x00e050) & intr0;
u32 stat1 = nvkm_rd32(device, 0x00e070) & intr1;
*lo = (stat1 & 0xffff0000) | (stat0 >> 16); *lo = (stat1 & 0xffff0000) | (stat0 >> 16);
*hi = (stat1 << 16) | (stat0 & 0x0000ffff); *hi = (stat1 << 16) | (stat0 & 0x0000ffff);
nv_wr32(gpio, 0x00e054, intr0); nvkm_wr32(device, 0x00e054, intr0);
nv_wr32(gpio, 0x00e074, intr1); nvkm_wr32(device, 0x00e074, intr1);
} }
void void
g94_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data) g94_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data)
{ {
u32 inte0 = nv_rd32(gpio, 0x00e050); struct nvkm_device *device = gpio->subdev.device;
u32 inte1 = nv_rd32(gpio, 0x00e070); u32 inte0 = nvkm_rd32(device, 0x00e050);
u32 inte1 = nvkm_rd32(device, 0x00e070);
if (type & NVKM_GPIO_LO) if (type & NVKM_GPIO_LO)
inte0 = (inte0 & ~(mask << 16)) | (data << 16); inte0 = (inte0 & ~(mask << 16)) | (data << 16);
if (type & NVKM_GPIO_HI) if (type & NVKM_GPIO_HI)
@ -51,8 +53,8 @@ g94_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data)
inte1 = (inte1 & ~(mask << 16)) | (data << 16); inte1 = (inte1 & ~(mask << 16)) | (data << 16);
if (type & NVKM_GPIO_HI) if (type & NVKM_GPIO_HI)
inte1 = (inte1 & ~mask) | data; inte1 = (inte1 & ~mask) | data;
nv_wr32(gpio, 0x00e050, inte0); nvkm_wr32(device, 0x00e050, inte0);
nv_wr32(gpio, 0x00e070, inte1); nvkm_wr32(device, 0x00e070, inte1);
} }
struct nvkm_oclass * struct nvkm_oclass *

15
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gf110.c
View File

@ -26,7 +26,8 @@
void void
gf110_gpio_reset(struct nvkm_gpio *gpio, u8 match) gf110_gpio_reset(struct nvkm_gpio *gpio, u8 match)
{ {
struct nvkm_bios *bios = nvkm_bios(gpio); struct nvkm_device *device = gpio->subdev.device;
struct nvkm_bios *bios = device->bios;
u8 ver, len; u8 ver, len;
u16 entry; u16 entry;
int ent = -1; int ent = -1;
@ -45,25 +46,27 @@ gf110_gpio_reset(struct nvkm_gpio *gpio, u8 match)
gpio->set(gpio, 0, func, line, defs); gpio->set(gpio, 0, func, line, defs);
nv_mask(gpio, 0x00d610 + (line * 4), 0xff, unk0); nvkm_mask(device, 0x00d610 + (line * 4), 0xff, unk0);
if (unk1--) if (unk1--)
nv_mask(gpio, 0x00d740 + (unk1 * 4), 0xff, line); nvkm_mask(device, 0x00d740 + (unk1 * 4), 0xff, line);
} }
} }
int int
gf110_gpio_drive(struct nvkm_gpio *gpio, int line, int dir, int out) gf110_gpio_drive(struct nvkm_gpio *gpio, int line, int dir, int out)
{ {
struct nvkm_device *device = gpio->subdev.device;
u32 data = ((dir ^ 1) << 13) | (out << 12); u32 data = ((dir ^ 1) << 13) | (out << 12);
nv_mask(gpio, 0x00d610 + (line * 4), 0x00003000, data); nvkm_mask(device, 0x00d610 + (line * 4), 0x00003000, data);
nv_mask(gpio, 0x00d604, 0x00000001, 0x00000001); /* update? */ nvkm_mask(device, 0x00d604, 0x00000001, 0x00000001); /* update? */
return 0; return 0;
} }
int int
gf110_gpio_sense(struct nvkm_gpio *gpio, int line) gf110_gpio_sense(struct nvkm_gpio *gpio, int line)
{ {
return !!(nv_rd32(gpio, 0x00d610 + (line * 4)) & 0x00004000); struct nvkm_device *device = gpio->subdev.device;
return !!(nvkm_rd32(device, 0x00d610 + (line * 4)) & 0x00004000);
} }
struct nvkm_oclass * struct nvkm_oclass *

22
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c
View File

@ -26,21 +26,23 @@
static void static void
gk104_gpio_intr_stat(struct nvkm_gpio *gpio, u32 *hi, u32 *lo) gk104_gpio_intr_stat(struct nvkm_gpio *gpio, u32 *hi, u32 *lo)
{ {
u32 intr0 = nv_rd32(gpio, 0x00dc00); struct nvkm_device *device = gpio->subdev.device;
u32 intr1 = nv_rd32(gpio, 0x00dc80); u32 intr0 = nvkm_rd32(device, 0x00dc00);
u32 stat0 = nv_rd32(gpio, 0x00dc08) & intr0; u32 intr1 = nvkm_rd32(device, 0x00dc80);
u32 stat1 = nv_rd32(gpio, 0x00dc88) & intr1; u32 stat0 = nvkm_rd32(device, 0x00dc08) & intr0;
u32 stat1 = nvkm_rd32(device, 0x00dc88) & intr1;
*lo = (stat1 & 0xffff0000) | (stat0 >> 16); *lo = (stat1 & 0xffff0000) | (stat0 >> 16);
*hi = (stat1 << 16) | (stat0 & 0x0000ffff); *hi = (stat1 << 16) | (stat0 & 0x0000ffff);
nv_wr32(gpio, 0x00dc00, intr0); nvkm_wr32(device, 0x00dc00, intr0);
nv_wr32(gpio, 0x00dc80, intr1); nvkm_wr32(device, 0x00dc80, intr1);
} }
void void
gk104_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data) gk104_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data)
{ {
u32 inte0 = nv_rd32(gpio, 0x00dc08); struct nvkm_device *device = gpio->subdev.device;
u32 inte1 = nv_rd32(gpio, 0x00dc88); u32 inte0 = nvkm_rd32(device, 0x00dc08);
u32 inte1 = nvkm_rd32(device, 0x00dc88);
if (type & NVKM_GPIO_LO) if (type & NVKM_GPIO_LO)
inte0 = (inte0 & ~(mask << 16)) | (data << 16); inte0 = (inte0 & ~(mask << 16)) | (data << 16);
if (type & NVKM_GPIO_HI) if (type & NVKM_GPIO_HI)
@ -51,8 +53,8 @@ gk104_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data)
inte1 = (inte1 & ~(mask << 16)) | (data << 16); inte1 = (inte1 & ~(mask << 16)) | (data << 16);
if (type & NVKM_GPIO_HI) if (type & NVKM_GPIO_HI)
inte1 = (inte1 & ~mask) | data; inte1 = (inte1 & ~mask) | data;
nv_wr32(gpio, 0x00dc08, inte0); nvkm_wr32(device, 0x00dc08, inte0);
nv_wr32(gpio, 0x00dc88, inte1); nvkm_wr32(device, 0x00dc88, inte1);
} }
struct nvkm_oclass * struct nvkm_oclass *

22
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c
View File

@ -28,19 +28,20 @@
static int static int
nv10_gpio_sense(struct nvkm_gpio *gpio, int line) nv10_gpio_sense(struct nvkm_gpio *gpio, int line)
{ {
struct nvkm_device *device = gpio->subdev.device;
if (line < 2) { if (line < 2) {
line = line * 16; line = line * 16;
line = nv_rd32(gpio, 0x600818) >> line; line = nvkm_rd32(device, 0x600818) >> line;
return !!(line & 0x0100); return !!(line & 0x0100);
} else } else
if (line < 10) { if (line < 10) {
line = (line - 2) * 4; line = (line - 2) * 4;
line = nv_rd32(gpio, 0x60081c) >> line; line = nvkm_rd32(device, 0x60081c) >> line;
return !!(line & 0x04); return !!(line & 0x04);
} else } else
if (line < 14) { if (line < 14) {
line = (line - 10) * 4; line = (line - 10) * 4;
line = nv_rd32(gpio, 0x600850) >> line; line = nvkm_rd32(device, 0x600850) >> line;
return !!(line & 0x04); return !!(line & 0x04);
} }
@ -50,6 +51,7 @@ nv10_gpio_sense(struct nvkm_gpio *gpio, int line)
static int static int
nv10_gpio_drive(struct nvkm_gpio *gpio, int line, int dir, int out) nv10_gpio_drive(struct nvkm_gpio *gpio, int line, int dir, int out)
{ {
struct nvkm_device *device = gpio->subdev.device;
u32 reg, mask, data; u32 reg, mask, data;
if (line < 2) { if (line < 2) {
@ -73,29 +75,31 @@ nv10_gpio_drive(struct nvkm_gpio *gpio, int line, int dir, int out)
return -EINVAL; return -EINVAL;
} }
nv_mask(gpio, reg, mask << line, data << line); nvkm_mask(device, reg, mask << line, data << line);
return 0; return 0;
} }
static void static void
nv10_gpio_intr_stat(struct nvkm_gpio *gpio, u32 *hi, u32 *lo) nv10_gpio_intr_stat(struct nvkm_gpio *gpio, u32 *hi, u32 *lo)
{ {
u32 intr = nv_rd32(gpio, 0x001104); struct nvkm_device *device = gpio->subdev.device;
u32 stat = nv_rd32(gpio, 0x001144) & intr; u32 intr = nvkm_rd32(device, 0x001104);
u32 stat = nvkm_rd32(device, 0x001144) & intr;
*lo = (stat & 0xffff0000) >> 16; *lo = (stat & 0xffff0000) >> 16;
*hi = (stat & 0x0000ffff); *hi = (stat & 0x0000ffff);
nv_wr32(gpio, 0x001104, intr); nvkm_wr32(device, 0x001104, intr);
} }
static void static void
nv10_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data) nv10_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data)
{ {
u32 inte = nv_rd32(gpio, 0x001144); struct nvkm_device *device = gpio->subdev.device;
u32 inte = nvkm_rd32(device, 0x001144);
if (type & NVKM_GPIO_LO) if (type & NVKM_GPIO_LO)
inte = (inte & ~(mask << 16)) | (data << 16); inte = (inte & ~(mask << 16)) | (data << 16);
if (type & NVKM_GPIO_HI) if (type & NVKM_GPIO_HI)
inte = (inte & ~mask) | data; inte = (inte & ~mask) | data;
nv_wr32(gpio, 0x001144, inte); nvkm_wr32(device, 0x001144, inte);
} }
struct nvkm_oclass * struct nvkm_oclass *

23
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c
View File

@ -26,7 +26,8 @@
void void
nv50_gpio_reset(struct nvkm_gpio *gpio, u8 match) nv50_gpio_reset(struct nvkm_gpio *gpio, u8 match)
{ {
struct nvkm_bios *bios = nvkm_bios(gpio); struct nvkm_device *device = gpio->subdev.device;
struct nvkm_bios *bios = device->bios;
u8 ver, len; u8 ver, len;
u16 entry; u16 entry;
int ent = -1; int ent = -1;
@ -49,7 +50,7 @@ nv50_gpio_reset(struct nvkm_gpio *gpio, u8 match)
gpio->set(gpio, 0, func, line, defs); gpio->set(gpio, 0, func, line, defs);
nv_mask(gpio, reg, 0x00010001 << lsh, val << lsh); nvkm_mask(device, reg, 0x00010001 << lsh, val << lsh);
} }
} }
@ -69,45 +70,49 @@ nv50_gpio_location(int line, u32 *reg, u32 *shift)
int int
nv50_gpio_drive(struct nvkm_gpio *gpio, int line, int dir, int out) nv50_gpio_drive(struct nvkm_gpio *gpio, int line, int dir, int out)
{ {
struct nvkm_device *device = gpio->subdev.device;
u32 reg, shift; u32 reg, shift;
if (nv50_gpio_location(line, &reg, &shift)) if (nv50_gpio_location(line, &reg, &shift))
return -EINVAL; return -EINVAL;
nv_mask(gpio, reg, 3 << shift, (((dir ^ 1) << 1) | out) << shift); nvkm_mask(device, reg, 3 << shift, (((dir ^ 1) << 1) | out) << shift);
return 0; return 0;
} }
int int
nv50_gpio_sense(struct nvkm_gpio *gpio, int line) nv50_gpio_sense(struct nvkm_gpio *gpio, int line)
{ {
struct nvkm_device *device = gpio->subdev.device;
u32 reg, shift; u32 reg, shift;
if (nv50_gpio_location(line, &reg, &shift)) if (nv50_gpio_location(line, &reg, &shift))
return -EINVAL; return -EINVAL;
return !!(nv_rd32(gpio, reg) & (4 << shift)); return !!(nvkm_rd32(device, reg) & (4 << shift));
} }
static void static void
nv50_gpio_intr_stat(struct nvkm_gpio *gpio, u32 *hi, u32 *lo) nv50_gpio_intr_stat(struct nvkm_gpio *gpio, u32 *hi, u32 *lo)
{ {
u32 intr = nv_rd32(gpio, 0x00e054); struct nvkm_device *device = gpio->subdev.device;
u32 stat = nv_rd32(gpio, 0x00e050) & intr; u32 intr = nvkm_rd32(device, 0x00e054);
u32 stat = nvkm_rd32(device, 0x00e050) & intr;
*lo = (stat & 0xffff0000) >> 16; *lo = (stat & 0xffff0000) >> 16;
*hi = (stat & 0x0000ffff); *hi = (stat & 0x0000ffff);
nv_wr32(gpio, 0x00e054, intr); nvkm_wr32(device, 0x00e054, intr);
} }
static void static void
nv50_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data) nv50_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data)
{ {
u32 inte = nv_rd32(gpio, 0x00e050); struct nvkm_device *device = gpio->subdev.device;
u32 inte = nvkm_rd32(device, 0x00e050);
if (type & NVKM_GPIO_LO) if (type & NVKM_GPIO_LO)
inte = (inte & ~(mask << 16)) | (data << 16); inte = (inte & ~(mask << 16)) | (data << 16);
if (type & NVKM_GPIO_HI) if (type & NVKM_GPIO_HI)
inte = (inte & ~mask) | data; inte = (inte & ~mask) | data;
nv_wr32(gpio, 0x00e050, inte); nvkm_wr32(device, 0x00e050, inte);
} }
struct nvkm_oclass * struct nvkm_oclass *