ARM: tegra: irq: Remove PM support
Tegra PM irq support is being improved, remove it for now until the rest of the platform gets PM support. Signed-off-by: Colin Cross <ccross@android.com>
This commit is contained in:
Colin Cross
Will Deacon
parent
938fa349fb
commit
4dda2d384b
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@ -27,9 +27,6 @@ int tegra_legacy_force_irq_status(unsigned int irq);
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void tegra_legacy_select_fiq(unsigned int irq, bool fiq);
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unsigned long tegra_legacy_vfiq(int nr);
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unsigned long tegra_legacy_class(int nr);
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int tegra_legacy_irq_set_wake(int irq, int enable);
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void tegra_legacy_irq_set_lp1_wake_mask(void);
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void tegra_legacy_irq_restore_mask(void);
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void tegra_init_legacy_irq(void);
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#endif
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@ -28,75 +28,9 @@
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#include <mach/iomap.h>
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#include <mach/legacy_irq.h>
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#include <mach/suspend.h>
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#include "board.h"
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#define PMC_CTRL 0x0
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#define PMC_CTRL_LATCH_WAKEUPS (1 << 5)
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#define PMC_WAKE_MASK 0xc
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#define PMC_WAKE_LEVEL 0x10
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#define PMC_WAKE_STATUS 0x14
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#define PMC_SW_WAKE_STATUS 0x18
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#define PMC_DPD_SAMPLE 0x20
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static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
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static u32 tegra_lp0_wake_enb;
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static u32 tegra_lp0_wake_level;
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static u32 tegra_lp0_wake_level_any;
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/* ensures that sufficient time is passed for a register write to
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* serialize into the 32KHz domain */
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static void pmc_32kwritel(u32 val, unsigned long offs)
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{
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writel(val, pmc + offs);
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udelay(130);
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}
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int tegra_set_lp1_wake(int irq, int enable)
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{
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return tegra_legacy_irq_set_wake(irq, enable);
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}
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void tegra_set_lp0_wake_pads(u32 wake_enb, u32 wake_level, u32 wake_any)
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{
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u32 temp;
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u32 status;
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u32 lvl;
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wake_level &= wake_enb;
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wake_any &= wake_enb;
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wake_level |= (tegra_lp0_wake_level & tegra_lp0_wake_enb);
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wake_any |= (tegra_lp0_wake_level_any & tegra_lp0_wake_enb);
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wake_enb |= tegra_lp0_wake_enb;
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pmc_32kwritel(0, PMC_SW_WAKE_STATUS);
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temp = readl(pmc + PMC_CTRL);
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temp |= PMC_CTRL_LATCH_WAKEUPS;
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pmc_32kwritel(temp, PMC_CTRL);
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temp &= ~PMC_CTRL_LATCH_WAKEUPS;
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pmc_32kwritel(temp, PMC_CTRL);
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status = readl(pmc + PMC_SW_WAKE_STATUS);
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lvl = readl(pmc + PMC_WAKE_LEVEL);
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/* flip the wakeup trigger for any-edge triggered pads
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* which are currently asserting as wakeups */
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lvl ^= status;
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lvl &= wake_any;
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wake_level |= lvl;
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writel(wake_level, pmc + PMC_WAKE_LEVEL);
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/* Enable DPD sample to trigger sampling pads data and direction
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* in which pad will be driven during lp0 mode*/
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writel(0x1, pmc + PMC_DPD_SAMPLE);
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writel(wake_enb, pmc + PMC_WAKE_MASK);
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}
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static void tegra_mask(struct irq_data *d)
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{
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if (d->irq >= 32)
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@ -49,9 +49,6 @@ static void __iomem *ictlr_reg_base[] = {
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IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
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};
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static u32 tegra_legacy_wake_mask[4];
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static u32 tegra_legacy_saved_mask[4];
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/* When going into deep sleep, the CPU is powered down, taking the GIC with it
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In order to wake, the wake interrupts need to be enabled in the legacy
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interrupt controller. */
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@ -129,40 +126,6 @@ unsigned long tegra_legacy_class(int nr)
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return readl(base + ICTLR_CPU_IEP_CLASS);
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}
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int tegra_legacy_irq_set_wake(int irq, int enable)
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{
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irq -= 32;
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if (enable)
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tegra_legacy_wake_mask[irq >> 5] |= 1 << (irq & 31);
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else
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tegra_legacy_wake_mask[irq >> 5] &= ~(1 << (irq & 31));
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return 0;
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}
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void tegra_legacy_irq_set_lp1_wake_mask(void)
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{
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void __iomem *base;
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int i;
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for (i = 0; i < NUM_ICTLRS; i++) {
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base = ictlr_reg_base[i];
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tegra_legacy_saved_mask[i] = readl(base + ICTLR_CPU_IER);
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writel(tegra_legacy_wake_mask[i], base + ICTLR_CPU_IER);
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}
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}
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void tegra_legacy_irq_restore_mask(void)
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{
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void __iomem *base;
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int i;
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for (i = 0; i < NUM_ICTLRS; i++) {
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base = ictlr_reg_base[i];
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writel(tegra_legacy_saved_mask[i], base + ICTLR_CPU_IER);
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}
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}
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void tegra_init_legacy_irq(void)
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{
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int i;
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@ -173,43 +136,3 @@ void tegra_init_legacy_irq(void)
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writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
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}
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}
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#ifdef CONFIG_PM
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static u32 cop_ier[NUM_ICTLRS];
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static u32 cpu_ier[NUM_ICTLRS];
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static u32 cpu_iep[NUM_ICTLRS];
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void tegra_irq_suspend(void)
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{
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unsigned long flags;
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int i;
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local_irq_save(flags);
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for (i = 0; i < NUM_ICTLRS; i++) {
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void __iomem *ictlr = ictlr_reg_base[i];
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cpu_ier[i] = readl(ictlr + ICTLR_CPU_IER);
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cpu_iep[i] = readl(ictlr + ICTLR_CPU_IEP_CLASS);
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cop_ier[i] = readl(ictlr + ICTLR_COP_IER);
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writel(~0, ictlr + ICTLR_COP_IER_CLR);
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}
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local_irq_restore(flags);
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}
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void tegra_irq_resume(void)
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{
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unsigned long flags;
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int i;
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local_irq_save(flags);
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for (i = 0; i < NUM_ICTLRS; i++) {
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void __iomem *ictlr = ictlr_reg_base[i];
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writel(cpu_iep[i], ictlr + ICTLR_CPU_IEP_CLASS);
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writel(~0ul, ictlr + ICTLR_CPU_IER_CLR);
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writel(cpu_ier[i], ictlr + ICTLR_CPU_IER_SET);
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writel(0, ictlr + ICTLR_COP_IEP_CLASS);
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writel(~0ul, ictlr + ICTLR_COP_IER_CLR);
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writel(cop_ier[i], ictlr + ICTLR_COP_IER_SET);
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}
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local_irq_restore(flags);
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}
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#endif
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