gpio: omap: use raw locks for locking
This patch converts gpio_bank.lock from a spin_lock into a
raw_spin_lock. The call path is to access this lock is always under a
raw_spin_lock, for instance
- __setup_irq() holds &desc->lock with irq off
+ __irq_set_trigger()
+ omap_gpio_irq_type()
- handle_level_irq() (runs with irqs off therefore raw locks)
+ mask_ack_irq()
+ omap_gpio_mask_irq()
This fixes the obvious backtrace on -RT. However the locking vs context
is not and this is not limited to -RT:
- omap_gpio_irq_type() is called with IRQ off and has an conditional
call to pm_runtime_get_sync() which may sleep. Either it may happen or
it may not happen but pm_runtime_get_sync() should not be called with
irqs off.
- omap_gpio_debounce() is holding the lock with IRQs off.
+ omap2_set_gpio_debounce()
+ clk_prepare_enable()
+ clk_prepare() this one might sleep.
The number of users of gpiod_set_debounce() / gpio_set_debounce()
looks low but still this is not good.
Acked-by: Javier Martinez Canillas <javier@dowhile0.org>
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Sebastian Andrzej Siewior
Linus Walleij
parent
d1aceb80c6
commit
4dbada2be4
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@ -57,7 +57,7 @@ struct gpio_bank {
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u32 saved_datain;
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u32 level_mask;
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u32 toggle_mask;
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spinlock_t lock;
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raw_spinlock_t lock;
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struct gpio_chip chip;
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struct clk *dbck;
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u32 mod_usage;
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@ -498,17 +498,17 @@ static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
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if (!BANK_USED(bank))
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pm_runtime_get_sync(bank->dev);
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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retval = omap_set_gpio_triggering(bank, offset, type);
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if (retval)
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goto error;
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omap_gpio_init_irq(bank, offset);
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if (!omap_gpio_is_input(bank, offset)) {
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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retval = -EINVAL;
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goto error;
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}
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
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irq_set_handler_locked(d, handle_level_irq);
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@ -634,14 +634,14 @@ static int omap_set_gpio_wakeup(struct gpio_bank *bank, unsigned offset,
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return -EINVAL;
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}
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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if (enable)
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bank->context.wake_en |= gpio_bit;
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else
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bank->context.wake_en &= ~gpio_bit;
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writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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@ -667,10 +667,10 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
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if (!BANK_USED(bank))
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pm_runtime_get_sync(bank->dev);
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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omap_enable_gpio_module(bank, offset);
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bank->mod_usage |= BIT(offset);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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@ -680,14 +680,14 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
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struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
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unsigned long flags;
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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bank->mod_usage &= ~(BIT(offset));
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if (!LINE_USED(bank->irq_usage, offset)) {
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omap_set_gpio_direction(bank, offset, 1);
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omap_clear_gpio_debounce(bank, offset);
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}
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omap_disable_gpio_module(bank, offset);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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/*
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* If this is the last gpio to be freed in the bank,
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@ -789,7 +789,7 @@ static unsigned int omap_gpio_irq_startup(struct irq_data *d)
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if (!BANK_USED(bank))
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pm_runtime_get_sync(bank->dev);
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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if (!LINE_USED(bank->mod_usage, offset))
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omap_set_gpio_direction(bank, offset, 1);
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@ -798,12 +798,12 @@ static unsigned int omap_gpio_irq_startup(struct irq_data *d)
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omap_enable_gpio_module(bank, offset);
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bank->irq_usage |= BIT(offset);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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omap_gpio_unmask_irq(d);
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return 0;
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err:
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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if (!BANK_USED(bank))
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pm_runtime_put(bank->dev);
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return -EINVAL;
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@ -815,7 +815,7 @@ static void omap_gpio_irq_shutdown(struct irq_data *d)
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unsigned long flags;
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unsigned offset = d->hwirq;
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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bank->irq_usage &= ~(BIT(offset));
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omap_set_gpio_irqenable(bank, offset, 0);
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omap_clear_gpio_irqstatus(bank, offset);
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@ -823,7 +823,7 @@ static void omap_gpio_irq_shutdown(struct irq_data *d)
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if (!LINE_USED(bank->mod_usage, offset))
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omap_clear_gpio_debounce(bank, offset);
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omap_disable_gpio_module(bank, offset);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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/*
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* If this is the last IRQ to be freed in the bank,
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@ -847,10 +847,10 @@ static void omap_gpio_mask_irq(struct irq_data *d)
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unsigned offset = d->hwirq;
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unsigned long flags;
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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omap_set_gpio_irqenable(bank, offset, 0);
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omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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}
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static void omap_gpio_unmask_irq(struct irq_data *d)
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@ -860,7 +860,7 @@ static void omap_gpio_unmask_irq(struct irq_data *d)
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u32 trigger = irqd_get_trigger_type(d);
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unsigned long flags;
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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if (trigger)
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omap_set_gpio_triggering(bank, offset, trigger);
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@ -872,7 +872,7 @@ static void omap_gpio_unmask_irq(struct irq_data *d)
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}
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omap_set_gpio_irqenable(bank, offset, 1);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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}
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/*---------------------------------------------------------------------*/
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@ -885,9 +885,9 @@ static int omap_mpuio_suspend_noirq(struct device *dev)
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OMAP_MPUIO_GPIO_MASKIT / bank->stride;
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unsigned long flags;
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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@ -900,9 +900,9 @@ static int omap_mpuio_resume_noirq(struct device *dev)
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OMAP_MPUIO_GPIO_MASKIT / bank->stride;
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unsigned long flags;
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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writel_relaxed(bank->context.wake_en, mask_reg);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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@ -948,9 +948,9 @@ static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
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bank = container_of(chip, struct gpio_bank, chip);
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reg = bank->base + bank->regs->direction;
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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dir = !!(readl_relaxed(reg) & BIT(offset));
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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return dir;
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}
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@ -960,9 +960,9 @@ static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
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unsigned long flags;
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bank = container_of(chip, struct gpio_bank, chip);
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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omap_set_gpio_direction(bank, offset, 1);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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@ -984,10 +984,10 @@ static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
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unsigned long flags;
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bank = container_of(chip, struct gpio_bank, chip);
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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bank->set_dataout(bank, offset, value);
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omap_set_gpio_direction(bank, offset, 0);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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@ -999,9 +999,9 @@ static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
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bank = container_of(chip, struct gpio_bank, chip);
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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omap2_set_gpio_debounce(bank, offset, debounce);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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@ -1012,9 +1012,9 @@ static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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unsigned long flags;
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bank = container_of(chip, struct gpio_bank, chip);
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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bank->set_dataout(bank, offset, value);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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}
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/*---------------------------------------------------------------------*/
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@ -1210,7 +1210,7 @@ static int omap_gpio_probe(struct platform_device *pdev)
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else
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bank->set_dataout = omap_set_gpio_dataout_mask;
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spin_lock_init(&bank->lock);
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raw_spin_lock_init(&bank->lock);
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/* Static mapping, never released */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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@ -1268,7 +1268,7 @@ static int omap_gpio_runtime_suspend(struct device *dev)
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unsigned long flags;
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u32 wake_low, wake_hi;
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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/*
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* Only edges can generate a wakeup event to the PRCM.
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@ -1321,7 +1321,7 @@ update_gpio_context_count:
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bank->get_context_loss_count(bank->dev);
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omap_gpio_dbck_disable(bank);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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@ -1336,7 +1336,7 @@ static int omap_gpio_runtime_resume(struct device *dev)
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unsigned long flags;
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int c;
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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/*
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* On the first resume during the probe, the context has not
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@ -1372,14 +1372,14 @@ static int omap_gpio_runtime_resume(struct device *dev)
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if (c != bank->context_loss_count) {
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omap_gpio_restore_context(bank);
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} else {
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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}
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}
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if (!bank->workaround_enabled) {
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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@ -1434,7 +1434,7 @@ static int omap_gpio_runtime_resume(struct device *dev)
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}
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bank->workaround_enabled = false;
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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