drm/amdgpu: Send Message to SMU on aldebaran passthrough for sbr handling
For Aldebaran chip passthrough case we need to intimate SMU about special handling for SBR.On older chips we send LightSBR to SMU, enabling the same for Aldebaran. Slight difference, compared to previous chips, is on Aldebaran, SMU would do a heavy reset on SBR. Hence, the word Heavy instead of Light SBR is used for SMU to differentiate. Reviewed by: Shaoyun.liu <Shaoyun.liu@amd.com> Signed-off-by: sashank saye <sashank.saye@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2619,11 +2619,10 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
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if (r)
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DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
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/* For XGMI + passthrough configuration on arcturus, enable light SBR */
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if (adev->asic_type == CHIP_ARCTURUS &&
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amdgpu_passthrough(adev) &&
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adev->gmc.xgmi.num_physical_nodes > 1)
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smu_set_light_sbr(&adev->smu, true);
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/* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */
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if (amdgpu_passthrough(adev) && ((adev->asic_type == CHIP_ARCTURUS && adev->gmc.xgmi.num_physical_nodes > 1)||
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adev->asic_type == CHIP_ALDEBARAN ))
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smu_handle_passthrough_sbr(&adev->smu, true);
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if (adev->gmc.xgmi.num_physical_nodes > 1) {
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mutex_lock(&mgpu_info.mutex);
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@ -102,7 +102,9 @@
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#define PPSMC_MSG_GfxDriverResetRecovery 0x42
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#define PPSMC_MSG_BoardPowerCalibration 0x43
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#define PPSMC_Message_Count 0x44
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#define PPSMC_MSG_HeavySBR 0x45
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#define PPSMC_Message_Count 0x46
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//PPSMC Reset Types
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#define PPSMC_RESET_TYPE_WARM_RESET 0x00
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@ -1257,9 +1257,9 @@ struct pptable_funcs {
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int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu);
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/**
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* @set_light_sbr: Set light sbr mode for the SMU.
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* @smu_handle_passthrough_sbr: Send message to SMU about special handling for SBR.
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*/
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int (*set_light_sbr)(struct smu_context *smu, bool enable);
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int (*smu_handle_passthrough_sbr)(struct smu_context *smu, bool enable);
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/**
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* @wait_for_event: Wait for events from SMU.
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@ -1415,7 +1415,7 @@ int smu_allow_xgmi_power_down(struct smu_context *smu, bool en);
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int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value);
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int smu_set_light_sbr(struct smu_context *smu, bool enable);
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int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable);
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int smu_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event,
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uint64_t event_arg);
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@ -229,7 +229,8 @@
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__SMU_DUMMY_MAP(BoardPowerCalibration), \
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__SMU_DUMMY_MAP(RequestGfxclk), \
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__SMU_DUMMY_MAP(ForceGfxVid), \
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__SMU_DUMMY_MAP(UnforceGfxVid),
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__SMU_DUMMY_MAP(UnforceGfxVid), \
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__SMU_DUMMY_MAP(HeavySBR),
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#undef __SMU_DUMMY_MAP
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#define __SMU_DUMMY_MAP(type) SMU_MSG_##type
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@ -312,7 +312,7 @@ int smu_v11_0_deep_sleep_control(struct smu_context *smu,
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void smu_v11_0_interrupt_work(struct smu_context *smu);
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int smu_v11_0_set_light_sbr(struct smu_context *smu, bool enable);
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int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable);
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int smu_v11_0_restore_user_od_settings(struct smu_context *smu);
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@ -3058,13 +3058,13 @@ static int smu_gfx_state_change_set(void *handle,
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return ret;
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}
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int smu_set_light_sbr(struct smu_context *smu, bool enable)
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int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)
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{
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int ret = 0;
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mutex_lock(&smu->mutex);
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if (smu->ppt_funcs->set_light_sbr)
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ret = smu->ppt_funcs->set_light_sbr(smu, enable);
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if (smu->ppt_funcs->smu_handle_passthrough_sbr)
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ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable);
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mutex_unlock(&smu->mutex);
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return ret;
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@ -2472,7 +2472,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
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.deep_sleep_control = smu_v11_0_deep_sleep_control,
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.get_fan_parameters = arcturus_get_fan_parameters,
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.interrupt_work = smu_v11_0_interrupt_work,
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.set_light_sbr = smu_v11_0_set_light_sbr,
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.smu_handle_passthrough_sbr = smu_v11_0_handle_passthrough_sbr,
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.set_mp1_state = smu_cmn_set_mp1_state,
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};
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@ -1724,7 +1724,7 @@ int smu_v11_0_mode1_reset(struct smu_context *smu)
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return ret;
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}
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int smu_v11_0_set_light_sbr(struct smu_context *smu, bool enable)
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int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable)
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{
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int ret = 0;
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@ -141,6 +141,7 @@ static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT
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MSG_MAP(SetUclkDpmMode, PPSMC_MSG_SetUclkDpmMode, 0),
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MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0),
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MSG_MAP(BoardPowerCalibration, PPSMC_MSG_BoardPowerCalibration, 0),
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MSG_MAP(HeavySBR, PPSMC_MSG_HeavySBR, 0),
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};
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static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = {
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@ -1912,6 +1913,14 @@ out:
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return ret;
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}
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static int aldebaran_smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)
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{
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int ret = 0;
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ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_HeavySBR, enable ? 1 : 0, NULL);
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return ret;
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}
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static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu)
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{
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#if 0
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@ -2021,6 +2030,7 @@ static const struct pptable_funcs aldebaran_ppt_funcs = {
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.get_gpu_metrics = aldebaran_get_gpu_metrics,
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.mode1_reset_is_support = aldebaran_is_mode1_reset_supported,
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.mode2_reset_is_support = aldebaran_is_mode2_reset_supported,
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.smu_handle_passthrough_sbr = aldebaran_smu_handle_passthrough_sbr,
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.mode1_reset = aldebaran_mode1_reset,
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.set_mp1_state = aldebaran_set_mp1_state,
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.mode2_reset = aldebaran_mode2_reset,
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