mfd: db8500 OPP and sleep handling update
This updates the operating point handling code by: - Supporting the DDR OPP retention state. - Supporting another low operating point named APE_50_PARTLY_25_OPP - Adding an interface to figure out if the sleep state change was properly achieved. Signed-off-by: Shreshtha Kumar Sahu <shreshthakumar.sahu@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Mattias Nilsson <mattias.i.nilsson@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This commit is contained in:
Mattias Nilsson
Samuel Ortiz
parent
992b133a5d
commit
4d64d2e34b
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@ -343,11 +343,13 @@ static struct {
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* mb1_transfer - state needed for mailbox 1 communication.
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* @lock: The transaction lock.
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* @work: The transaction completion structure.
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* @ape_opp: The current APE OPP.
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* @ack: Reply ("acknowledge") data.
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*/
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static struct {
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struct mutex lock;
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struct completion work;
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u8 ape_opp;
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struct {
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u8 header;
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u8 arm_opp;
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@ -816,6 +818,11 @@ int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
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return 0;
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}
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u8 db8500_prcmu_get_power_state_result(void)
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{
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return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
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}
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/* This function should only be called while mb0_transfer.lock is held. */
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static void config_wakeups(void)
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{
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@ -965,6 +972,52 @@ int db8500_prcmu_set_ddr_opp(u8 opp)
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return 0;
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}
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/* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
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static void request_even_slower_clocks(bool enable)
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{
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void __iomem *clock_reg[] = {
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PRCM_ACLK_MGT,
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PRCM_DMACLK_MGT
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};
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unsigned long flags;
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unsigned int i;
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spin_lock_irqsave(&clk_mgt_lock, flags);
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/* Grab the HW semaphore. */
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while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
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cpu_relax();
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for (i = 0; i < ARRAY_SIZE(clock_reg); i++) {
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u32 val;
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u32 div;
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val = readl(clock_reg[i]);
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div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
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if (enable) {
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if ((div <= 1) || (div > 15)) {
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pr_err("prcmu: Bad clock divider %d in %s\n",
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div, __func__);
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goto unlock_and_return;
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}
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div <<= 1;
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} else {
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if (div <= 2)
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goto unlock_and_return;
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div >>= 1;
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}
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val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
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(div & PRCM_CLK_MGT_CLKPLLDIV_MASK));
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writel(val, clock_reg[i]);
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}
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unlock_and_return:
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/* Release the HW semaphore. */
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writel(0, PRCM_SEM);
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spin_unlock_irqrestore(&clk_mgt_lock, flags);
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}
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/**
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* db8500_set_ape_opp - set the appropriate APE OPP
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* @opp: The new APE operating point to which transition is to be made
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@ -976,14 +1029,24 @@ int db8500_prcmu_set_ape_opp(u8 opp)
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{
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int r = 0;
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if (opp == mb1_transfer.ape_opp)
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return 0;
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mutex_lock(&mb1_transfer.lock);
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if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)
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request_even_slower_clocks(false);
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if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP))
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goto skip_message;
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while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
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cpu_relax();
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writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
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writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
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writeb(opp, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
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writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp),
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(tcdm_base + PRCM_REQ_MB1_APE_OPP));
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writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
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wait_for_completion(&mb1_transfer.work);
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@ -992,6 +1055,13 @@ int db8500_prcmu_set_ape_opp(u8 opp)
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(mb1_transfer.ack.ape_opp != opp))
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r = -EIO;
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skip_message:
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if ((!r && (opp == APE_50_PARTLY_25_OPP)) ||
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(r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)))
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request_even_slower_clocks(true);
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if (!r)
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mb1_transfer.ape_opp = opp;
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mutex_unlock(&mb1_transfer.lock);
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return r;
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@ -2631,6 +2701,7 @@ void __init db8500_prcmu_early_init(void)
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init_completion(&mb0_transfer.ac_wake_work);
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mutex_init(&mb1_transfer.lock);
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init_completion(&mb1_transfer.work);
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mb1_transfer.ape_opp = APE_NO_CHANGE;
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mutex_init(&mb2_transfer.lock);
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init_completion(&mb2_transfer.work);
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spin_lock_init(&mb2_transfer.auto_pm_lock);
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@ -457,6 +457,25 @@ enum hw_acc_dev {
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NUM_HW_ACC
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};
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/**
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* enum prcmu_power_status - results from set_power_state
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* @PRCMU_SLEEP_OK: Sleep went ok
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* @PRCMU_DEEP_SLEEP_OK: DeepSleep went ok
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* @PRCMU_IDLE_OK: Idle went ok
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* @PRCMU_DEEPIDLE_OK: DeepIdle went ok
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* @PRCMU_PRCMU2ARMPENDINGIT_ER: Pending interrupt detected
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* @PRCMU_ARMPENDINGIT_ER: Pending interrupt detected
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*
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*/
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enum prcmu_power_status {
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PRCMU_SLEEP_OK = 0xf3,
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PRCMU_DEEP_SLEEP_OK = 0xf6,
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PRCMU_IDLE_OK = 0xf0,
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PRCMU_DEEPIDLE_OK = 0xe3,
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PRCMU_PRCMU2ARMPENDINGIT_ER = 0x91,
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PRCMU_ARMPENDINGIT_ER = 0x93,
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};
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/*
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* Definitions for autonomous power management configuration.
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*/
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@ -544,6 +563,7 @@ int db8500_prcmu_load_a9wdog(u8 id, u32 val);
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void db8500_prcmu_system_reset(u16 reset_code);
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int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
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u8 db8500_prcmu_get_power_state_result(void);
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void db8500_prcmu_enable_wakeups(u32 wakeups);
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int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
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int db8500_prcmu_request_clock(u8 clock, bool enable);
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@ -699,6 +719,11 @@ static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
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return 0;
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}
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static inline u8 db8500_prcmu_get_power_state_result(void)
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{
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return 0;
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}
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static inline void db8500_prcmu_enable_wakeups(u32 wakeups) {}
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static inline int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
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@ -185,12 +185,14 @@ enum prcmu_clock {
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* @APE_NO_CHANGE: The APE operating point is unchanged
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* @APE_100_OPP: The new APE operating point is ape100opp
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* @APE_50_OPP: 50%
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* @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%.
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*/
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enum ape_opp {
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APE_OPP_INIT = 0x00,
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APE_NO_CHANGE = 0x01,
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APE_100_OPP = 0x02,
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APE_50_OPP = 0x03
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APE_50_OPP = 0x03,
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APE_50_PARTLY_25_OPP = 0xFF,
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};
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/**
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@ -271,6 +273,14 @@ static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
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keep_ap_pll);
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}
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static inline u8 prcmu_get_power_state_result(void)
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{
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if (cpu_is_u5500())
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return -EINVAL;
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else
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return db8500_prcmu_get_power_state_result();
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}
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static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
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{
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if (cpu_is_u5500())
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@ -663,9 +673,10 @@ static inline int prcmu_stop_temp_sense(void)
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/* PRCMU QoS APE OPP class */
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#define PRCMU_QOS_APE_OPP 1
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#define PRCMU_QOS_DDR_OPP 2
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#define PRCMU_QOS_ARM_OPP 3
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#define PRCMU_QOS_DEFAULT_VALUE -1
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#ifdef CONFIG_UX500_PRCMU_QOS_POWER
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#ifdef CONFIG_DBX500_PRCMU_QOS_POWER
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unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
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void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
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