ARM: tegra20: Store CPU "resettable" status in IRAM
Commit7232398abc("ARM: tegra: Convert PMC to a driver") changed tegra_resume() location storing from late to early and, as a result, broke suspend on Tegra20. PMC scratch register 41 is used by tegra LP1 resume code for retrieving stored physical memory address of common resume function and in the same time used by tegra20_cpu_shutdown() (shared by Tegra20 cpuidle driver and platform SMP code), which is storing CPU1 "resettable" status. It implies strict order of scratch register usage, otherwise resume function address is lost on Tegra20 after disabling non-boot CPU's on suspend. Fix it by storing "resettable" status in IRAM instead of PMC scratch register. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Fixes:7232398abc(ARM: tegra: Convert PMC to a driver) Cc: <stable@vger.kernel.org> # v3.17+ Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Dmitry Osipenko
Thierry Reding
parent
039aa4d680
commit
4d48edb3c3
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@ -34,6 +34,7 @@
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#include "iomap.h"
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#include "irq.h"
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#include "pm.h"
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#include "reset.h"
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#include "sleep.h"
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#ifdef CONFIG_PM_SLEEP
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@ -70,15 +71,13 @@ static struct cpuidle_driver tegra_idle_driver = {
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#ifdef CONFIG_PM_SLEEP
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#ifdef CONFIG_SMP
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static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
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static int tegra20_reset_sleeping_cpu_1(void)
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{
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int ret = 0;
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tegra_pen_lock();
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if (readl(pmc + PMC_SCRATCH41) == CPU_RESETTABLE)
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if (readb(tegra20_cpu1_resettable_status) == CPU_RESETTABLE)
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tegra20_cpu_shutdown(1);
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else
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ret = -EINVAL;
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@ -169,10 +169,10 @@ after_errata:
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cmp r6, #TEGRA20
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bne 1f
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/* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
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mov32 r5, TEGRA_PMC_BASE
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mov r0, #0
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mov32 r5, TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET
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mov r0, #CPU_NOT_RESETTABLE
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cmp r10, #0
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strne r0, [r5, #PMC_SCRATCH41]
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strneb r0, [r5, #__tegra20_cpu1_resettable_status_offset]
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1:
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#endif
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@ -281,6 +281,10 @@ __tegra_cpu_reset_handler_data:
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.rept TEGRA_RESET_DATA_SIZE
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.long 0
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.endr
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.globl __tegra20_cpu1_resettable_status_offset
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.equ __tegra20_cpu1_resettable_status_offset, \
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. - __tegra_cpu_reset_handler_start
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.byte 0
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.align L1_CACHE_SHIFT
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ENTRY(__tegra_cpu_reset_handler_end)
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@ -35,6 +35,7 @@ extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
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void __tegra_cpu_reset_handler_start(void);
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void __tegra_cpu_reset_handler(void);
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void __tegra20_cpu1_resettable_status_offset(void);
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void __tegra_cpu_reset_handler_end(void);
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void tegra_secondary_startup(void);
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@ -47,6 +48,9 @@ void tegra_secondary_startup(void);
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(IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
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((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \
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(u32)__tegra_cpu_reset_handler_start)))
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#define tegra20_cpu1_resettable_status \
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(IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
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(u32)__tegra20_cpu1_resettable_status_offset))
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#endif
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#define tegra_cpu_reset_handler_offset \
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@ -97,9 +97,10 @@ ENDPROC(tegra20_hotplug_shutdown)
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ENTRY(tegra20_cpu_shutdown)
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cmp r0, #0
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reteq lr @ must not be called for CPU 0
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mov32 r1, TEGRA_PMC_VIRT + PMC_SCRATCH41
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mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT
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ldr r2, =__tegra20_cpu1_resettable_status_offset
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mov r12, #CPU_RESETTABLE
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str r12, [r1]
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strb r12, [r1, r2]
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cpu_to_halt_reg r1, r0
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ldr r3, =TEGRA_FLOW_CTRL_VIRT
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@ -182,38 +183,41 @@ ENDPROC(tegra_pen_unlock)
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/*
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* tegra20_cpu_clear_resettable(void)
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*
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* Called to clear the "resettable soon" flag in PMC_SCRATCH41 when
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* Called to clear the "resettable soon" flag in IRAM variable when
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* it is expected that the secondary CPU will be idle soon.
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*/
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ENTRY(tegra20_cpu_clear_resettable)
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mov32 r1, TEGRA_PMC_VIRT + PMC_SCRATCH41
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mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT
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ldr r2, =__tegra20_cpu1_resettable_status_offset
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mov r12, #CPU_NOT_RESETTABLE
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str r12, [r1]
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strb r12, [r1, r2]
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ret lr
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ENDPROC(tegra20_cpu_clear_resettable)
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/*
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* tegra20_cpu_set_resettable_soon(void)
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*
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* Called to set the "resettable soon" flag in PMC_SCRATCH41 when
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* Called to set the "resettable soon" flag in IRAM variable when
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* it is expected that the secondary CPU will be idle soon.
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*/
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ENTRY(tegra20_cpu_set_resettable_soon)
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mov32 r1, TEGRA_PMC_VIRT + PMC_SCRATCH41
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mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT
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ldr r2, =__tegra20_cpu1_resettable_status_offset
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mov r12, #CPU_RESETTABLE_SOON
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str r12, [r1]
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strb r12, [r1, r2]
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ret lr
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ENDPROC(tegra20_cpu_set_resettable_soon)
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/*
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* tegra20_cpu_is_resettable_soon(void)
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*
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* Returns true if the "resettable soon" flag in PMC_SCRATCH41 has been
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* Returns true if the "resettable soon" flag in IRAM variable has been
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* set because it is expected that the secondary CPU will be idle soon.
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*/
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ENTRY(tegra20_cpu_is_resettable_soon)
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mov32 r1, TEGRA_PMC_VIRT + PMC_SCRATCH41
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ldr r12, [r1]
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mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT
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ldr r2, =__tegra20_cpu1_resettable_status_offset
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ldrb r12, [r1, r2]
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cmp r12, #CPU_RESETTABLE_SOON
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moveq r0, #1
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movne r0, #0
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@ -256,9 +260,10 @@ ENTRY(tegra20_sleep_cpu_secondary_finish)
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mov r0, #TEGRA_FLUSH_CACHE_LOUIS
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bl tegra_disable_clean_inv_dcache
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mov32 r0, TEGRA_PMC_VIRT + PMC_SCRATCH41
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mov32 r0, TEGRA_IRAM_RESET_BASE_VIRT
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ldr r4, =__tegra20_cpu1_resettable_status_offset
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mov r3, #CPU_RESETTABLE
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str r3, [r0]
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strb r3, [r0, r4]
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bl tegra_cpu_do_idle
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@ -274,10 +279,10 @@ ENTRY(tegra20_sleep_cpu_secondary_finish)
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bl tegra_pen_lock
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mov32 r3, TEGRA_PMC_VIRT
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add r0, r3, #PMC_SCRATCH41
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mov32 r0, TEGRA_IRAM_RESET_BASE_VIRT
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ldr r4, =__tegra20_cpu1_resettable_status_offset
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mov r3, #CPU_NOT_RESETTABLE
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str r3, [r0]
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strb r3, [r0, r4]
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bl tegra_pen_unlock
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@ -18,6 +18,7 @@
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#define __MACH_TEGRA_SLEEP_H
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#include "iomap.h"
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#include "irammap.h"
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#define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
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+ IO_CPU_VIRT)
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@ -29,6 +30,9 @@
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+ IO_APB_VIRT)
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#define TEGRA_PMC_VIRT (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT)
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#define TEGRA_IRAM_RESET_BASE_VIRT (IO_IRAM_VIRT + \
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TEGRA_IRAM_RESET_HANDLER_OFFSET)
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/* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */
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#define PMC_SCRATCH37 0x130
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#define PMC_SCRATCH38 0x134
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