mei: me: make mei_me_fw_sku_sps_4() less cryptic
Last add mei_me_fw_sku_sps_4() kdoc and add descriptive defines for register name and values. Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Link: https://lore.kernel.org/r/20200619165121.2145330-3-tomas.winkler@intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -106,6 +106,8 @@
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/* Host Firmware Status Registers in PCI Config Space */
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#define PCI_CFG_HFS_1 0x40
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# define PCI_CFG_HFS_1_D0I3_MSK 0x80000000
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# define PCI_CFG_HFS_1_OPMODE_MSK 0xf0000 /* OP MODE Mask: SPS <= 4.0 */
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# define PCI_CFG_HFS_1_OPMODE_SPS 0xf0000 /* SPS SKU : SPS <= 4.0 */
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#define PCI_CFG_HFS_2 0x48
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#define PCI_CFG_HFS_3 0x60
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# define PCI_CFG_HFS_3_FW_SKU_MSK 0x00000070
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@ -1366,20 +1366,26 @@ static bool mei_me_fw_type_nm(const struct pci_dev *pdev)
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#define MEI_CFG_FW_NM \
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.quirk_probe = mei_me_fw_type_nm
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/**
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* mei_me_fw_sku_sps_4() - check for sps 4.0 sku
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*
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* Read ME FW Status register to check for SPS Firmware.
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* The SPS FW is only signaled in the PCI function 0.
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* __Note__: Deprecated by SPS 5.0 and newer.
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*
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* @pdev: pci device
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*
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* Return: true in case of SPS firmware
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*/
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static bool mei_me_fw_type_sps_4(const struct pci_dev *pdev)
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{
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u32 reg;
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unsigned int devfn;
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/*
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* Read ME FW Status register to check for SPS Firmware
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* The SPS FW is only signaled in pci function 0
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*/
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devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0);
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pci_bus_read_config_dword(pdev->bus, devfn, PCI_CFG_HFS_1, ®);
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trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg);
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/* if bits [19:16] = 15, running SPS Firmware */
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return (reg & 0xf0000) == 0xf0000;
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return (reg & PCI_CFG_HFS_1_OPMODE_MSK) == PCI_CFG_HFS_1_OPMODE_SPS;
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}
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#define MEI_CFG_FW_SPS_4 \
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