Qualcomm dts updates for v5.15
This introduces the MSM8226 platform and an initial dts for the Samsung Galaxy S III Neo phone. MSM8974 gains another UART and this is used to enable Bluetooth on the Sony Xperia Z2 Tablet. Samsung Galaxy S5 gains regulator definitions for audio and modem remoteprocs, effectively enabling these. DSI clocks on APQ8064 are updates as the old legacy clock names are no longer supported by the driver. And IPQ806x GMAC nodes gains AHB resets wired up. Lastly APQ8060 is converted to a SPDX header and the ethernet node is updates in accordance with the binding. -----BEGIN PGP SIGNATURE----- iQJPBAABCAA5FiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmEa1W8bHGJqb3JuLmFu ZGVyc3NvbkBsaW5hcm8ub3JnAAoJEAsfOT8Nma3F0CcP/1rCgNZKQ++chXeDJX7O BL1EmmHZ93RiY/u9etmwT2ZzLhGwIiEPhddqL/a1B2J4VFCfjsJVy31XQbYBCWpN cZtsnsV0mHD9oU/SpHEAUkllTXZlr4kNoghaynzipQCC9oirZw7m4MxiSJENczZ9 sGefAzqpNtvGjR07wKUraWFJXDqKYQg1b+Tfu0Q1p3T9ZivkP3gRL4MGt4dzTgwo tFHCs6bR9FA+eChmMhVfsBSytdOC+Y6kGOQOJLrvDYmHEkA2H3hLmkKAWpbGtjw2 Y4aj8n3IqPEkl2rSuH1pu2av5DwfDI4Kf+VI4LSz7/WVJ1e+FkrOQpCSTCOb+1m1 8re+do1wHB5PE3mnmvLa6avFO/GnKU9Uex8n+vPwUQ03Dhvh6IZ9jKo007iNrXB9 3VobOwkxPfVIUHv+T23pfbTHyWzcTZzLXivZSNQ9p3hfqBHS8dIwMJ9XMRW8M55D BSoaEt5kHOKZMlgcpHFczeZiART/x6NkaIOU0b3TDq4xeSRttnKEr/ehy45jNN0w yE7YG82gCuBBsI2pIre3mxVf8J8y10UBoE1plcKrDpJT80Xcik0llgfAvULw3Jx3 l4GGGlKFZSqzQ70B+4R8kfN5pLCI06CobEWL6VvZW9wfndt2M9NO/iPv/tRNAvVc gsD+CKQ5QLVywIr/tZZ2d+EY =JynD -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmEbgcEACgkQmmx57+YA GNlC0Q//USmb8u05Sn7DlYu46UBcNcQrgGOCXIrNWkERm7jxEhUqp4soI24jomiq 1GEKWApzPlmLtBvQKiGl5IoCypYbZ0kOyFBP+FYezmSD8vCU46UtnzKV+b3mzwQH rDPFogjj92LBv1+i+8jgry3tvrdK3oM2QJ2cSIF7EyXjuMBok36zXdPpG4mP8dBT vla+IZFa7GXOi+SKVykB8tlaGPaslamIfG6ZtjeJJuGsPRDotjmjc9vvGEtKfOF0 cHKKTtPli60NqwHX61UURNAcaoURBw4W4Jy0KolvMWo98I+TyWf18xRF2aanm8pa mLsK7SlqipRY1ofTeHZwb6eK3j13qD5knv+tWjjwCTCmAufljnLwqoP494mHeU5D ppLMcSfw9HheR/J3NoimcJ8mvWe2/NOmtqxKFt0QYUiL3p0uqZUfclTUbIUEqzi3 v30lFh984aB91HgLQkl3dgqmCG/ggS7gy1W2BEQZtsaQHAW4v+psYAjMMMGpkcZV vHjWffic3y+mVgClZ8PRaqkXQB/IjfuoSF/+VT6/kTNosmOXkvphd3je2ogE9Zn8 4r+ALaAlmaRLpBzvfDTyNAB2gUi4ar22JVa5VpF1y4G9SAlHkv6TdpnaTgfw4SKu D3fqjSlYJ6DL7CRB+4BetPn2Al83CvuPXSMRF9iuikllRGHZfbs= =zDwv -----END PGP SIGNATURE----- Merge tag 'qcom-dts-for-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt Qualcomm dts updates for v5.15 This introduces the MSM8226 platform and an initial dts for the Samsung Galaxy S III Neo phone. MSM8974 gains another UART and this is used to enable Bluetooth on the Sony Xperia Z2 Tablet. Samsung Galaxy S5 gains regulator definitions for audio and modem remoteprocs, effectively enabling these. DSI clocks on APQ8064 are updates as the old legacy clock names are no longer supported by the driver. And IPQ806x GMAC nodes gains AHB resets wired up. Lastly APQ8060 is converted to a SPDX header and the ethernet node is updates in accordance with the binding. * tag 'qcom-dts-for-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: ARM: dts: qcom: add ahb reset to ipq806x-gmac ARM: dts: qcom: Fix up APQ8060 DragonBoard license ARM: dts: qcom: msm8974: castor: Add Bluetooth-related nodes ARM: dts: qcom: msm8974: Add blsp2_uart7 for bluetooth on sirius ARM: dts: qcom: Add initial DTS file for Samsung Galaxy S III Neo phone dt-bindings: arm: qcom: Document MSM8226 SoC binding ARM: dts: qcom: Add support for MSM8226 SoC ARM: dts: qcom: apq8060: Correct Ethernet node name and drop bogus irq property ARM: dts: qcom: apq8064: correct clock names ARM: dts: qcom: msm8974-klte: Enable remote processors Link: https://lore.kernel.org/r/20210816211957.579365-1-bjorn.andersson@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
4d314179d6
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@ -31,6 +31,7 @@ description: |
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ipq6018
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ipq8074
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mdm9615
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msm8226
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msm8916
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msm8974
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msm8992
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@ -114,6 +115,11 @@ properties:
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- qcom,apq8084-sbc
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- const: qcom,apq8084
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- items:
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- enum:
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- samsung,s3ve3g
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- const: qcom,msm8226
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- items:
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- enum:
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- qcom,msm8960-cdp
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@ -957,6 +957,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
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qcom-ipq4019-ap.dk07.1-c2.dtb \
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qcom-ipq8064-ap148.dtb \
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qcom-ipq8064-rb3011.dtb \
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qcom-msm8226-samsung-s3ve3g.dtb \
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qcom-msm8660-surf.dtb \
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qcom-msm8960-cdp.dtb \
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qcom-msm8974-fairphone-fp2.dtb \
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@ -1,25 +1,4 @@
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/*
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* Copyright 2016 Linaro Ltd
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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// SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
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@ -1262,9 +1262,9 @@
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<&mmcc DSI1_BYTE_CLK>,
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<&mmcc DSI_PIXEL_CLK>,
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<&mmcc DSI1_ESC_CLK>;
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clock-names = "iface_clk", "bus_clk", "core_mmss_clk",
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"src_clk", "byte_clk", "pixel_clk",
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"core_clk";
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clock-names = "iface", "bus", "core_mmss",
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"src", "byte", "pixel",
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"core";
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assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
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<&mmcc DSI1_ESC_SRC>,
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@ -980,8 +980,9 @@
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clocks = <&gcc GMAC_CORE1_CLK>;
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clock-names = "stmmaceth";
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resets = <&gcc GMAC_CORE1_RESET>;
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reset-names = "stmmaceth";
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resets = <&gcc GMAC_CORE1_RESET>,
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<&gcc GMAC_AHB_RESET>;
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reset-names = "stmmaceth", "ahb";
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status = "disabled";
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};
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@ -1003,8 +1004,9 @@
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clocks = <&gcc GMAC_CORE2_CLK>;
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clock-names = "stmmaceth";
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resets = <&gcc GMAC_CORE2_RESET>;
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reset-names = "stmmaceth";
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resets = <&gcc GMAC_CORE2_RESET>,
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<&gcc GMAC_AHB_RESET>;
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reset-names = "stmmaceth", "ahb";
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status = "disabled";
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};
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@ -1026,8 +1028,9 @@
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clocks = <&gcc GMAC_CORE3_CLK>;
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clock-names = "stmmaceth";
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resets = <&gcc GMAC_CORE3_RESET>;
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reset-names = "stmmaceth";
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resets = <&gcc GMAC_CORE3_RESET>,
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<&gcc GMAC_AHB_RESET>;
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reset-names = "stmmaceth", "ahb";
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status = "disabled";
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};
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@ -1049,8 +1052,9 @@
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clocks = <&gcc GMAC_CORE4_CLK>;
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clock-names = "stmmaceth";
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resets = <&gcc GMAC_CORE4_RESET>;
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reset-names = "stmmaceth";
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resets = <&gcc GMAC_CORE4_RESET>,
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<&gcc GMAC_AHB_RESET>;
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reset-names = "stmmaceth", "ahb";
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status = "disabled";
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};
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|
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@ -0,0 +1,25 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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#include "qcom-msm8226.dtsi"
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/ {
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model = "Samsung Galaxy S III Neo";
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compatible = "samsung,s3ve3g", "qcom,msm8226";
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aliases {
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serial0 = &blsp1_uart3;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&soc {
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serial@f991f000 {
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status = "ok";
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};
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};
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@ -0,0 +1,147 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-msm8974.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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chosen { };
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0>;
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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intc: interrupt-controller@f9000000 {
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compatible = "qcom,msm-qgic2";
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reg = <0xf9000000 0x1000>,
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<0xf9002000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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gcc: clock-controller@fc400000 {
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compatible = "qcom,gcc-msm8226";
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reg = <0xfc400000 0x4000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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tlmm: pinctrl@fd510000 {
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compatible = "qcom,msm8226-pinctrl";
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reg = <0xfd510000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 117>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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};
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blsp1_uart3: serial@f991f000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0xf991f000 0x1000>;
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interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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restart@fc4ab000 {
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compatible = "qcom,pshold";
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reg = <0xfc4ab000 0x4>;
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};
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rng@f9bff000 {
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compatible = "qcom,prng";
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reg = <0xf9bff000 0x200>;
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clocks = <&gcc GCC_PRNG_AHB_CLK>;
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clock-names = "core";
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};
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timer@f9020000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0xf9020000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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frame@f9021000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf9021000 0x1000>,
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<0xf9022000 0x1000>;
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};
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frame@f9023000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf9023000 0x1000>;
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status = "disabled";
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};
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frame@f9024000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf9024000 0x1000>;
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status = "disabled";
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};
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frame@f9025000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf9025000 0x1000>;
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status = "disabled";
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};
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frame@f9026000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf9026000 0x1000>;
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status = "disabled";
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};
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frame@f9027000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf9027000 0x1000>;
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status = "disabled";
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};
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frame@f9028000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf9028000 0x1000>;
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status = "disabled";
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};
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 2
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(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 3
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(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 4
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(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 1
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(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
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};
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};
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@ -315,6 +315,10 @@
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};
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/delete-node/ vreg-boost;
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adsp-pil {
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cx-supply = <&pma8084_s2>;
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};
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};
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&soc {
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@ -831,6 +835,13 @@
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vddio-supply = <&pma8084_l12>;
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};
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};
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remoteproc@fc880000 {
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cx-supply = <&pma8084_s2>;
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mss-supply = <&pma8084_s6>;
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mx-supply = <&pma8084_s1>;
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pll-supply = <&pma8084_l12>;
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};
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};
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&spmi_bus {
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|
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@ -11,6 +11,7 @@
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aliases {
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serial0 = &blsp1_uart2;
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serial1 = &blsp2_uart7;
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};
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chosen {
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@ -336,6 +337,27 @@
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pinctrl-0 = <&blsp1_uart2_pin_a>;
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};
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serial@f995d000 {
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status = "ok";
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pinctrl-names = "default";
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pinctrl-0 = <&blsp2_uart7_pin_a>;
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bluetooth {
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compatible = "brcm,bcm43438-bt";
|
||||
max-speed = <3000000>;
|
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||||
pinctrl-names = "default";
|
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pinctrl-0 = <&bt_host_wake_pin>,
|
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<&bt_dev_wake_pin>,
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<&bt_reg_on_pin>;
|
||||
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host-wakeup-gpios = <&msmgpio 95 GPIO_ACTIVE_HIGH>;
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device-wakeup-gpios = <&msmgpio 96 GPIO_ACTIVE_HIGH>;
|
||||
shutdown-gpios = <&pm8941_gpios 16 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@f9a55000 {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -380,6 +402,40 @@
|
|||
};
|
||||
};
|
||||
|
||||
blsp2_uart7_pin_a: blsp2-uart7-pin-active {
|
||||
tx {
|
||||
pins = "gpio41";
|
||||
function = "blsp_uart7";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
rx {
|
||||
pins = "gpio42";
|
||||
function = "blsp_uart7";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
cts {
|
||||
pins = "gpio43";
|
||||
function = "blsp_uart7";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
rts {
|
||||
pins = "gpio44";
|
||||
function = "blsp_uart7";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c8_pins: i2c8 {
|
||||
mux {
|
||||
pins = "gpio47", "gpio48";
|
||||
|
|
@ -479,6 +535,23 @@
|
|||
input-enable;
|
||||
};
|
||||
};
|
||||
|
||||
bt_host_wake_pin: bt-host-wake {
|
||||
pins = "gpio95";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
output-low;
|
||||
};
|
||||
|
||||
bt_dev_wake_pin: bt-dev-wake {
|
||||
pins = "gpio96";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@f9964000 {
|
||||
|
|
@ -606,6 +679,14 @@
|
|||
power-source = <PM8941_GPIO_S3>;
|
||||
};
|
||||
|
||||
bt_reg_on_pin: bt-reg-on {
|
||||
pins = "gpio16";
|
||||
function = "normal";
|
||||
|
||||
output-low;
|
||||
power-source = <PM8941_GPIO_S3>;
|
||||
};
|
||||
|
||||
wlan_sleep_clk_pin: wl-sleep-clk {
|
||||
pins = "gpio17";
|
||||
function = "func2";
|
||||
|
|
|
|||
|
|
@ -715,6 +715,15 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp2_uart7: serial@f995d000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0xf995d000 0x1000>;
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_NONE>;
|
||||
clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp2_uart8: serial@f995e000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0xf995e000 0x1000>;
|
||||
|
|
|
|||
Loading…
Reference in New Issue