x86: Fix a handful of typos
Fix a couple of typos in code comments. [ bp: While at it: s/IRQ's/IRQs/. ] Signed-off-by: Martin Molnar <martin.molnar.programming@gmail.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Link: https://lkml.kernel.org/r/0819a044-c360-44a4-f0b6-3f5bafe2d35c@gmail.com
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@ -84,7 +84,7 @@ void __init init_IRQ(void)
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* On cpu 0, Assign ISA_IRQ_VECTOR(irq) to IRQ 0..15.
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* On cpu 0, Assign ISA_IRQ_VECTOR(irq) to IRQ 0..15.
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* If these IRQ's are handled by legacy interrupt-controllers like PIC,
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* If these IRQ's are handled by legacy interrupt-controllers like PIC,
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* then this configuration will likely be static after the boot. If
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* then this configuration will likely be static after the boot. If
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* these IRQ's are handled by more mordern controllers like IO-APIC,
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* these IRQs are handled by more modern controllers like IO-APIC,
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* then this vector space can be freed and re-used dynamically as the
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* then this vector space can be freed and re-used dynamically as the
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* irq's migrate etc.
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* irq's migrate etc.
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*/
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*/
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@ -403,9 +403,9 @@ static void default_do_nmi(struct pt_regs *regs)
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* a 'real' unknown NMI. For example, while processing
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* a 'real' unknown NMI. For example, while processing
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* a perf NMI another perf NMI comes in along with a
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* a perf NMI another perf NMI comes in along with a
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* 'real' unknown NMI. These two NMIs get combined into
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* 'real' unknown NMI. These two NMIs get combined into
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* one (as descibed above). When the next NMI gets
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* one (as described above). When the next NMI gets
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* processed, it will be flagged by perf as handled, but
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* processed, it will be flagged by perf as handled, but
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* noone will know that there was a 'real' unknown NMI sent
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* no one will know that there was a 'real' unknown NMI sent
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* also. As a result it gets swallowed. Or if the first
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* also. As a result it gets swallowed. Or if the first
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* perf NMI returns two events handled then the second
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* perf NMI returns two events handled then the second
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* NMI will get eaten by the logic below, again losing a
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* NMI will get eaten by the logic below, again losing a
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@ -531,7 +531,7 @@ static void emergency_vmx_disable_all(void)
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/*
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/*
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* We need to disable VMX on all CPUs before rebooting, otherwise
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* We need to disable VMX on all CPUs before rebooting, otherwise
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* we risk hanging up the machine, because the CPU ignore INIT
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* we risk hanging up the machine, because the CPU ignores INIT
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* signals when VMX is enabled.
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* signals when VMX is enabled.
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*
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*
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* We can't take any locks and we may be on an inconsistent
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* We can't take any locks and we may be on an inconsistent
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@ -1434,7 +1434,7 @@ early_param("possible_cpus", _setup_possible_cpus);
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/*
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/*
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* cpu_possible_mask should be static, it cannot change as cpu's
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* cpu_possible_mask should be static, it cannot change as cpu's
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* are onlined, or offlined. The reason is per-cpu data-structures
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* are onlined, or offlined. The reason is per-cpu data-structures
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* are allocated by some modules at init time, and dont expect to
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* are allocated by some modules at init time, and don't expect to
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* do this dynamically on cpu arrival/departure.
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* do this dynamically on cpu arrival/departure.
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* cpu_present_mask on the other hand can change dynamically.
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* cpu_present_mask on the other hand can change dynamically.
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* In case when cpu_hotplug is not compiled, then we resort to current
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* In case when cpu_hotplug is not compiled, then we resort to current
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@ -477,7 +477,7 @@ static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
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* transition from one expected value to another with a fairly
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* transition from one expected value to another with a fairly
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* high accuracy, and we didn't miss any events. We can thus
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* high accuracy, and we didn't miss any events. We can thus
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* use the TSC value at the transitions to calculate a pretty
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* use the TSC value at the transitions to calculate a pretty
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* good value for the TSC frequencty.
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* good value for the TSC frequency.
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*/
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*/
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static inline int pit_verify_msb(unsigned char val)
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static inline int pit_verify_msb(unsigned char val)
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{
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{
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@ -295,7 +295,7 @@ static cycles_t check_tsc_warp(unsigned int timeout)
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* But as the TSC is per-logical CPU and can potentially be modified wrongly
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* But as the TSC is per-logical CPU and can potentially be modified wrongly
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* by the bios, TSC sync test for smaller duration should be able
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* by the bios, TSC sync test for smaller duration should be able
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* to catch such errors. Also this will catch the condition where all the
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* to catch such errors. Also this will catch the condition where all the
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* cores in the socket doesn't get reset at the same time.
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* cores in the socket don't get reset at the same time.
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*/
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*/
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static inline unsigned int loop_timeout(int cpu)
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static inline unsigned int loop_timeout(int cpu)
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{
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{
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