UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

Two small fixes for SNI machines 

-----BEGIN PGP SIGNATURE-----
 
 iQJOBAABCAA4FiEEbt46xwy6kEcDOXoUeZbBVTGwZHAFAl9jdMIaHHRzYm9nZW5k
 QGFscGhhLmZyYW5rZW4uZGUACgkQeZbBVTGwZHDqPw/9HmZMfw1SbeGz+6umlh+Q
 jSV5YXCYWUqUWs1YtSzxS+7HjC/dPW86NbRgAEBN+KPxImDhIMJHI9EMixsUmw5J
 oh6V/OuGDLyQzO2qHkyQQHOIRYtFvOg9VH5Ha7BgGkaofR1IMQEfd5LwUipE8YKA
 4j9t/394s5iMpSc2vYJ3sRDTolHIWXk8GLE7R15Ujfi/DNRcs3/0XAGQxQjAUyWN
 Sa6glZPDYFdL2+XYH3cQPcZN9vk6N6qLAewx6j8dTRmzng/f1xy9cBAk3jH3mGh7
 l2zVYHqERGhycc8xr8I2jAniqc4wTDNAvpZ/ZnaVJlC9HnctHPiH3fGwPCeF3qdW
 w4oq32652GesrWy78raO+HBJ6oRGF1TczX0rrl58ZSvbkt7uC9DeKlcKAwc0mO/z
 j/1J0tziNmfvYUum/lW1ceTb8q4gRu152x0jjall82sc4bPGCpGm5T4wbWSqB1e6
 qPCn3AEDjP3xBsbzNBz6UTykfFgFNAhBqLQH2OZkw85JmQKpN7ViFXuT7ncDoz6p
 qHow7Hg3wZjejpS6BUU4dzZEfB8w5N/i+4IeSO9ZrGU7dt6djP2enI9V+yaYb3US
 ErbbVGXteIZK0qczdQCgNR6otOohR/0FaMRki9eVZva2JIhLzTC6ca68EEKRGcS5
 b4E0uJILYkNS+z95GcyMrZw=
 =E3mo
 -----END PGP SIGNATURE-----

Merge tag 'mips_fixes_5.9_2' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS fixes from Thomas Bogendoerfer:
 "Two small fixes for SNI machines"

* tag 'mips_fixes_5.9_2' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
  MIPS: SNI: Fix spurious interrupts
  MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT
This commit is contained in:
Linus Torvalds 2020-09-17 11:30:36 -07:00
parent 5ef64cc898 b959b97860
commit 4cbffc461e
2 changed files with 8 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/mips/Kconfig
View File

@ -877,6 +877,7 @@ config SNI_RM
select I8253
select I8259
select ISA
select MIPS_L1_CACHE_SHIFT_6
select SWAP_IO_SPACE if CPU_BIG_ENDIAN
select SYS_HAS_CPU_R4X00
select SYS_HAS_CPU_R5000

9
arch/mips/sni/a20r.c
View File

@ -143,7 +143,10 @@ static struct platform_device sc26xx_pdev = {
},
};
static u32 a20r_ack_hwint(void)
/*
* Trigger chipset to update CPU's CAUSE IP field
*/
static u32 a20r_update_cause_ip(void)
{
u32 status = read_c0_status();
@ -205,12 +208,14 @@ static void a20r_hwint(void)
int irq;
clear_c0_status(IE_IRQ0);
status = a20r_ack_hwint();
status = a20r_update_cause_ip();
cause = read_c0_cause();
irq = ffs(((cause & status) >> 8) & 0xf8);
if (likely(irq > 0))
do_IRQ(SNI_A20R_IRQ_BASE + irq - 1);
a20r_update_cause_ip();
set_c0_status(IE_IRQ0);
}