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arm64: tegra: Device tree changes for v5.8-rc1 

This contains a couple of fixes for minor issues, enables XUDC support
 on Tegra194, and enables EMC frequency scaling and video capture on
 Tegra210.
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Merge tag 'tegra-for-5.8-arm64-dt-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

arm64: tegra: Device tree changes for v5.8-rc1

This contains a couple of fixes for minor issues, enables XUDC support
on Tegra194, and enables EMC frequency scaling and video capture on
Tegra210.

* tag 'tegra-for-5.8-arm64-dt-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  arm64: tegra: Make the RTC a wakeup source on Jetson Nano and TX1
  arm64: tegra: Make the RTC a wakeup source on Jetson TX2
  arm64: tegra: Enable VI I2C on Jetson Nano
  arm64: tegra: Fix flag for 64-bit resources in 'ranges' property
  arm64: tegra: Add Tegra VI CSI support in device tree
  arm64: tegra: Add reset-cells to memory controller
  arm64: tegra: Fix SOR powergate clocks and reset
  arm64: tegra: Allow the PMIC RTC to wakeup Jetson Xavier
  arm64: tegra: Fix ethernet phy-mode for Jetson Xavier
  arm64: tegra: Hook up EMC cooling device
  arm64: tegra: Add external memory controller node for Tegra210
  arm64: tegra: Add XUDC node on Tegra194
  arm64: tegra: Kill off "simple-panel" compatibles

Link: https://lore.kernel.org/r/20200522142846.2376224-3-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2020-05-26 00:21:15 +02:00
parent 34a07a8da3 358a6777f5
commit 4cafc5d9c9
8 changed files with 130 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm64/boot/dts/nvidia/tegra132-norrin.dts
View File

@ -990,7 +990,7 @@
};
panel: panel {
compatible = "innolux,n116bge", "simple-panel";
compatible = "innolux,n116bge";
backlight = <&backlight>;
ddc-i2c-bus = <&dpaux>;
};

3
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
View File

@ -221,7 +221,8 @@
compatible = "maxim,max77620";
reg = <0x3c>;
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pmc>;
interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
#interrupt-cells = <2>;
interrupt-controller;

5
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
View File

@ -33,7 +33,7 @@
phy-reset-gpios = <&gpio TEGRA194_MAIN_GPIO(G, 5) GPIO_ACTIVE_LOW>;
phy-handle = <&phy>;
phy-mode = "rgmii";
phy-mode = "rgmii-id";
mdio {
#address-cells = <1>;
@ -111,7 +111,8 @@
compatible = "maxim,max20024";
reg = <0x3c>;
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pmc>;
interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
#interrupt-cells = <2>;
interrupt-controller;

30
arch/arm64/boot/dts/nvidia/tegra194.dtsi
View File

@ -644,6 +644,24 @@
};
};
usb@3550000 {
compatible = "nvidia,tegra194-xudc";
reg = <0x03550000 0x8000>,
<0x03558000 0x1000>;
reg-names = "base", "fpci";
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>,
<&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
<&bpmp TEGRA194_CLK_XUSB_SS>,
<&bpmp TEGRA194_CLK_XUSB_FS>;
clock-names = "dev", "ss", "ss_src", "fs_src";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
<&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
power-domain-names = "dev", "ss";
nvidia,xusb-padctl = <&xusb_padctl>;
status = "disabled";
};
usb@3610000 {
compatible = "nvidia,tegra194-xusb";
reg = <0x03610000 0x40000>,
@ -1387,7 +1405,7 @@
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */
0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */
0xc3000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */
0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
};
@ -1432,7 +1450,7 @@
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */
0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */
0xc3000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */
0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
};
@ -1477,7 +1495,7 @@
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */
0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */
0xc3000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */
0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
};
@ -1522,7 +1540,7 @@
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */
0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
0xc3000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
};
@ -1567,7 +1585,7 @@
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */
0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
0xc3000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
};
@ -1616,7 +1634,7 @@
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */
0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
0xc3000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
};

3
arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
View File

@ -38,7 +38,8 @@
pmic: pmic@3c {
compatible = "maxim,max77620";
reg = <0x3c>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&tegra_pmc>;
interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
#interrupt-cells = <2>;
interrupt-controller;

10
arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
View File

@ -14,6 +14,16 @@
status = "okay";
};
vi@54080000 {
status = "okay";
avdd-dsi-csi-supply = <&vdd_dsi_csi>;
csi@838 {
status = "okay";
};
};
sor@54580000 {
status = "okay";

7
arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
View File

@ -90,6 +90,10 @@
dpaux@545c0000 {
status = "okay";
};
i2c@546c0000 {
status = "okay";
};
};
gpu@57000000 {
@ -145,7 +149,8 @@
pmic: pmic@3c {
compatible = "maxim,max77620";
reg = <0x3c>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&tegra_pmc>;
interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
#interrupt-cells = <2>;
interrupt-controller;

89
arch/arm64/boot/dts/nvidia/tegra210.dtsi
View File

@ -137,9 +137,44 @@
vi@54080000 {
compatible = "nvidia,tegra210-vi";
reg = <0x0 0x54080000 0x0 0x00040000>;
reg = <0x0 0x54080000 0x0 0x700>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
clocks = <&tegra_car TEGRA210_CLK_VI>;
power-domains = <&pd_venc>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x54080000 0x2000>;
csi@838 {
compatible = "nvidia,tegra210-csi";
reg = <0x838 0x1300>;
status = "disabled";
assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
<&tegra_car TEGRA210_CLK_CILCD>,
<&tegra_car TEGRA210_CLK_CILE>,
<&tegra_car TEGRA210_CLK_CSI_TPG>;
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_PLL_P>;
assigned-clock-rates = <102000000>,
<102000000>,
<102000000>,
<972000000>;
clocks = <&tegra_car TEGRA210_CLK_CSI>,
<&tegra_car TEGRA210_CLK_CILAB>,
<&tegra_car TEGRA210_CLK_CILCD>,
<&tegra_car TEGRA210_CLK_CILE>,
<&tegra_car TEGRA210_CLK_CSI_TPG>;
clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
power-domains = <&pd_sor>;
};
};
tsec@54100000 {
@ -796,7 +831,9 @@
pd_sor: sor {
clocks = <&tegra_car TEGRA210_CLK_SOR0>,
<&tegra_car TEGRA210_CLK_SOR1>,
<&tegra_car TEGRA210_CLK_CSI>,
<&tegra_car TEGRA210_CLK_CILAB>,
<&tegra_car TEGRA210_CLK_CILCD>,
<&tegra_car TEGRA210_CLK_CILE>,
<&tegra_car TEGRA210_CLK_DSIA>,
<&tegra_car TEGRA210_CLK_DSIB>,
<&tegra_car TEGRA210_CLK_DPAUX>,
@ -804,7 +841,6 @@
<&tegra_car TEGRA210_CLK_MIPI_CAL>;
resets = <&tegra_car TEGRA210_CLK_SOR0>,
<&tegra_car TEGRA210_CLK_SOR1>,
<&tegra_car TEGRA210_CLK_CSI>,
<&tegra_car TEGRA210_CLK_DSIA>,
<&tegra_car TEGRA210_CLK_DSIB>,
<&tegra_car TEGRA210_CLK_DPAUX>,
@ -838,6 +874,15 @@
reset-names = "vic";
#power-domain-cells = <0>;
};
pd_venc: venc {
clocks = <&tegra_car TEGRA210_CLK_VI>,
<&tegra_car TEGRA210_CLK_CSI>;
resets = <&mc TEGRA210_MC_RESET_VI>,
<&tegra_car 20>,
<&tegra_car 52>;
#power-domain-cells = <0>;
};
};
sdmmc1_3v3: sdmmc1-3v3 {
@ -893,6 +938,19 @@
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
#reset-cells = <1>;
};
emc: external-memory-controller@7001b000 {
compatible = "nvidia,tegra210-emc";
reg = <0x0 0x7001b000 0x0 0x1000>,
<0x0 0x7001e000 0x0 0x1000>,
<0x0 0x7001f000 0x0 0x1000>;
clocks = <&tegra_car TEGRA210_CLK_EMC>;
clock-names = "emc";
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
nvidia,memory-controller = <&mc>;
#cooling-cells = <2>;
};
sata@70020000 {
@ -1550,6 +1608,18 @@
<&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
trips {
dram_nominal: mem-nominal-trip {
temperature = <50000>;
hysteresis = <1000>;
type = "passive";
};
dram_throttle: mem-throttle-trip {
temperature = <70000>;
hysteresis = <1000>;
type = "active";
};
mem-shutdown-trip {
temperature = <103000>;
hysteresis = <0>;
@ -1558,10 +1628,15 @@
};
cooling-maps {
/*
* There are currently no cooling maps,
* because there are no cooling devices.
*/
dram-passive {
cooling-device = <&emc 0 0>;
trip = <&dram_nominal>;
};
dram-active {
cooling-device = <&emc 1 1>;
trip = <&dram_throttle>;
};
};
};